Abov MC96F6432S Series User Manual

140
MC96F6432S
ABOV Semiconductor Co., Ltd.
11.8.2 8-bit Timer/Counter 3, 4 Mode
The 8-bit timer/counter mode is selected by control register as shown in Figure 11.30.
The two 8-bit timers have each counter and data register. The counter register is increased by internal or external
clock input.Timer 3 can use the input clock with one of 2, 4, 8, 32, 128, 512, 2048 and EC3prescaler division rates
(T3CK[2:0]). Timer 4 can use the input clock with one of 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192,
16384 and timer 3 clock prescaler division rates (T4CK[3:0]). When the value of T3CNT, T4CNT and T3DR, T4DR are
respectively identical in Timer 3, 4, the interrupt Timer 3, 4 occurs.
The external clock (EC3) counts up the timer at the rising edge. If the EC3 is selected as a clock source by T3CK[2:0],
EC3 port should be set to the input port by P00IO bit. Timer 4 can’t use the external EC3 clock.
T3EN
T3CR
1
ADDRESS:1000H (ESFR)
INITIAL VALUE : 0000_0000B
–
T3MS T3CK2 T3CK1 T3CK0 T3CN T3ST
–
0 X X X X X
16BIT
T4CR
0
ADDRESS:1002H (ESFR)
INITIAL VALUE : 0000_0000B
T4MS T4CN T4ST T4CK3 T4CK2 T4CK1 T4CK0
0 X X
X
X X X
P
r
e
s
c
a
l
e
r
fx
M
U
X
fx/2
T3CNT (8Bit)
EC3
fx/4
fx/8
fx/32
fx/128
fx/512
fx/2048
3
T3CK[2:0]
T3CN
8-bit Timer 3 Counter
T3DR (8Bit)
Comparator
T3IFR
To interrupt
block
T3O
8-bit Timer 3 Data Register
INT_ACK
Clear
Clear
Match
T3ST
T4CNT (8Bit)
4
T4CK[3:0]
8-bit Timer 4 Counter
T4DR (8Bit)
Comparator
To interrupt
block
T4O
8-bit Timer 4 Data Register
Clear
Match
T4ST
P
r
e
s
c
a
l
e
r
fx
M
U
X
fx/1
fx/2
fx/4
fx/8
fx/16384
T4CN
NOTE)
1. Do not set to “1111b” in the T4CK[3:0], when two 8-bit timer 3/4 modes.
Figure 11.30 8-bit Timer/Counter Mode for Timer 3, 4

Abov MC96F6432S Series Specifications

General

Brand	Abov
Model	MC96F6432S Series
Category	Microcontrollers
Language	English