Abov MC96F6432S Series - Block Diagram

98
MC96F6432S
ABOV Semiconductor Co., Ltd.
11.1.2 Block Diagram
Clock
Change
System
Clock Gen.
SCLK
(Core, System,
Peripheral)
fx
BIT
WDT
BIT
overflow
XIN
XOUT
Main OSC
fXIN
STOP Mode
XCLKE
Internal RC OSC
(16MHz)
STOP Mode
IRCE
fIRC
1/1
1/2
1/4
1/8
M
U
X
WDTRC OSC
(5kHz)
WDTCK
Stabilization Time
Generation
M
U
X
BIT clock
WDT clock
SXIN
SXOUT
Sub OSC
fSUB
STOP Mode
SCLKE
WT
2
SCLK[1:0]
/256
1/16
1/32
3
IRCS[2:0]
fx/4096
fx/1024
fx/128
fx/16
M
U
X
2
BITCK[1:0]
Figure 11.1 Clock Generator Block Diagram