Abov MC96F6432S Series User Manual

251
MC96F6432S
ABOV Semiconductor Co., Ltd.
14.2.2.3 Start and Stop Condition
Figure 14.5 Start and Stop Condition
14.2.2.4 Acknowledge Bit
Figure 14.6 Acknowledge on the Serial Bus
Figure 14.7 Clock Synchronization during Wait Procedure
Start wait
start HIGH
Host PC
DSCL OUT
Target
Device
DSCL OUT
DSCL
wait HIGH
Maximum
5 T
SCLK
Internal Operation
Acknowledge bit
transmission
minimum 1 T
SCLK
for next byte
transmission
Acknowledge bit
transmission
Minimum
500ns
1
9
2
10
Data output
By transmitter
Data output
By receiver
DSCL from
master
clock pulse for acknowledgement
no acknowledge
acknowledge
St
Sp
START condition
STOP condition
DSDA
DSCL
DSDA
DSCL

Abov MC96F6432S Series Specifications

General

Brand	Abov
Model	MC96F6432S Series
Category	Microcontrollers
Language	English