Abov MC96F6432S Series User Manual

209
MC96F6432S
ABOV Semiconductor Co., Ltd.
11.12.24 Register Description for USIn
USInBD (USIn Baud- Rate Generation Register: For UART and SPI mode): E3H/F3H, n = 0, 1
7
6
5
4
3
2
1
0
USInBD7
USInBD 6
USInBD 5
USInBD 4
USInBD 3
USInBD 2
USInBD 1
USInBD 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: FFH
USInBD[7:0]
The value in this register is used to generate internal baud rate in asynchronous
mode or to generate SCKn clock in SPI mode. To prevent malfunction, do not write
‘0’ in asynchronous mode and do not write ‘0’ or ‘1’ in SPI mode.
NOTE)
1. In common with USInSAR register, USInBD register is used for
slave address register when the USIn I2C mode.
USInDR (USIn Data Register: For UART, SPI, and I2C mode): E5H/F5H, n = 0, 1
7
6
5
4
3
2
1
0
USInDR7
USInDR 6
USInDR 5
USInDR 4
USInDR 3
USInDR 2
USInDR 1
USInDR 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 00H
USInDR[7:0]
The USIn transmit buffer and receive buffer share the same I/O address with this
DATA register. The transmit data buffer is the destination for data written to the
USInDR register. Reading the USInDR register returns the contents of the receive
buffer.
Write to this register only when the DREn flag is set. In SPI master mode, the SCK
clock is generated when data are written to this register.

Abov MC96F6432S Series Specifications

General

Brand	Abov
Model	MC96F6432S Series
Category	Microcontrollers
Language	English