Abov MC96F6432S Series User Manual

210
MC96F6432S
ABOV Semiconductor Co., Ltd.
USInSDHR (USInSDA Hold Time Register: For I2C mode): E4H/F4H, n = 0, 1
7
6
5
4
3
2
1
0
USInSDHR7
USInSDHR6
USInSDHR5
USInSDHR 4
USInSDHR 3
USInSDHR 2
USInSDHR 1
USInSDHR 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 01H
USInSDHR[7:0]
The register is used to control SDAn output timing from the falling edge of SCI in I2C
mode.
NOTE)
1. That SDAn is changed after t
SCLK
X (USInSDHR+2), in master
SDAn change in the middle of SCLn.
2. In slave mode, configure this register regarding the frequency of
SCLn from master.
3. The SDAn is changed after t
SCLK
X (USInSDHR+2) in master mode.
So, to insure operation in slave mode, the value
4. t
SCLK
X (USInSDHR+2) must be smaller than the period of SCL.
USInSCHR (USInSCL High Period Register: For I2C mode): E7H/F7H, n = 0, 1
7
6
5
4
3
2
1
0
USInSCHR7
USInSCHR6
USInSCHR5
USInSCHR 4
USInSCHR 3
USInSCHR 2
USInSCHR 1
USInSCHR 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value: 3FH
USInSCHR[7:0]
This register defines the high period of SCLn when it operates in I2C master mode.
The base clock is SCLK, the system clock, and the period is calculated by the
formula: t
SCLK
X (4 X USInSCHR +2) where
t
SCLK
is the period of SCLK.
So, the operating frequency of I2C master mode is calculated by the following equation.
f
I2C
=
t
SCLK
X (4 X (USInSCLR + USInSCHR) + 4)
1

Abov MC96F6432S Series Specifications

General

Brand	Abov
Model	MC96F6432S Series
Category	Microcontrollers
Language	English