Abov MC96F6432S Series - Page 257

257
MC96F6432S
ABOV Semiconductor Co., Ltd.
FMCR (Flash Mode Control Register): FEH
7
6
5
4
3
2
1
0
FMBUSY
–
–
–
–
FMCR2
FMCR1
FMCR0
R
–
–
–
–
R/W
R/W
R/W
Initial value: 00H
FMBUSY
Flash Mode Busy Bit. This bit will be used for only debugger.
0
No effect when “1” is written
1
Busy
FMCR[2:0]
Flash Mode Control Bits. During a flash mode operation, the CPU is hold and the
global interrupt is on disable state regardless of the IE.7 (EA) bit.
FMCR2
FMCR1
FMCR0
Description
0
0
1
Select flash page buffer reset mode
and start regardless of the FIDR
value (Clear all 64bytes to ‘0’)
0
1
0
Select flash sector erase mode and
start operation when the
FIDR=”10100101b’
0
1
1
Select flash sector write mode and
start operation when the
FIDR=”10100101b’
1
0
0
Select flash sector Code Write Protection and
Start operation when the
FIDR=”10100101b’
Others Values: No operation
(These bits are automatically cleared to logic ‘00H’ immediately after one time
operation)