Abov MC96F6432S Series - Page 279

279
MC96F6432S
ABOV Semiconductor Co., Ltd.
9 I/O Ports .................................................................................................................................................................. 61
9.1 I/O Ports ............................................................................................................................................................ 61
9.2 Port Register ..................................................................................................................................................... 61
9.2.1 Data Register (Px) ..................................................................................................................................... 61
9.2.2 Direction Register (PxIO) .......................................................................................................................... 61
9.2.3 Pull-up Resistor Selection Register (PxPU) .............................................................................................. 61
9.2.4 Open-drain Selection Register (PxOD) ..................................................................................................... 61
9.2.5 De-bounce Enable Register (PxDB) .......................................................................................................... 61
9.2.6 Port Function Selection Register (PxFSR) ................................................................................................ 62
9.2.7 Register Map ............................................................................................................................................. 62
9.3 P0 Port .............................................................................................................................................................. 63
9.3.1 P0 Port Description.................................................................................................................................... 63
9.3.2 Register description for P0 ........................................................................................................................ 63
9.4 P1 Port .............................................................................................................................................................. 67
9.4.1 P1 Port Description.................................................................................................................................... 67
9.4.2 Register description for P1 ........................................................................................................................ 67
9.5 P2 Port .............................................................................................................................................................. 71
9.5.1 P2 Port Description.................................................................................................................................... 71
9.5.2 Register description for P2 ........................................................................................................................ 71
9.6 P3 Port .............................................................................................................................................................. 74
9.6.1 P3 Port Description.................................................................................................................................... 74
9.6.2 Register description for P3 ........................................................................................................................ 74
9.7 P4 Port .............................................................................................................................................................. 76
9.7.1 P4 Port Description.................................................................................................................................... 76
9.7.2 Register description for P4 ........................................................................................................................ 76
9.8 P5 Port .............................................................................................................................................................. 78
9.8.1 P5 Port Description.................................................................................................................................... 78
9.8.2 Register description for P5 ........................................................................................................................ 78
10 Interrupt Controller ............................................................................................................................................ 80
10.1 Overview ........................................................................................................................................................... 80
10.2 External Interrupt .............................................................................................................................................. 82
10.3 Block Diagram .................................................................................................................................................. 83
10.4 Interrupt Vector Table ........................................................................................................................................ 84
10.5 Interrupt Sequence ........................................................................................................................................... 85
10.6 Effective Timing after Controlling Interrupt Bit .................................................................................................. 86
10.7 Multi Interrupt .................................................................................................................................................... 87
10.8 Interrupt Enable Accept Timing ......................................................................................................................... 88
10.9 Interrupt Service Routine Address .................................................................................................................... 88
10.10 Saving/Restore General-Purpose Registers ................................................................................................. 88
10.11 Interrupt Timing ............................................................................................................................................. 89
10.12 Interrupt Register Overview .......................................................................................................................... 89
10.12.1 Interrupt Enable Register (IE, IE1, IE2, IE3) .......................................................................................... 89
10.12.2 Interrupt Priority Register (IP, IP1) ......................................................................................................... 89
10.12.3 External Interrupt Flag Register (EIFLAG0, EIFLAG1) .......................................................................... 90
10.12.4 External Interrupt Polarity Register (EIPOL0L, EIPOL0H, EIPOL1) ...................................................... 90
10.12.5 Register Map .......................................................................................................................................... 90
10.12.6 Interrupt Register Description ................................................................................................................ 90
10.12.7 Register Description for Interrupt ........................................................................................................... 91
11 Peripheral Hardware .......................................................................................................................................... 97
11.1 Clock Generator ................................................................................................................................................ 97
11.1.1 Overview .................................................................................................................................................... 97
11.1.2 Block Diagram ........................................................................................................................................... 98
11.1.3 Register Map ............................................................................................................................................. 99
11.1.4 Clock Generator Register Description ....................................................................................................... 99
11.1.5 Register Description for Clock Generator ................................................................................................. 99
11.2 Basic Interval Timer ........................................................................................................................................ 101
11.2.1 Overview .................................................................................................................................................. 101
11.2.2 Block Diagram ......................................................................................................................................... 101