11.13.5 Block Diagram ...................................................................................................................................... 227
11.13.6 Register Map ........................................................................................................................................ 227
11.13.7 LCD Driver Register Description .......................................................................................................... 227
11.13.8 Register Description for LCD Driver .................................................................................................... 228
12 Power Down Operation .................................................................................................................................... 231
12.1 Overview ......................................................................................................................................................... 231
12.2 Peripheral Operation in IDLE/STOP Mode ..................................................................................................... 231
12.3 IDLE Mode ...................................................................................................................................................... 232
12.4 STOP Mode .................................................................................................................................................... 233
12.5 Release Operation of STOP Mode ................................................................................................................. 234
12.6 Register Map .................................................................................................................................................. 235
12.7 Power Down Operation Register Description ................................................................................................. 235
12.8 Register Description for Power Down Operation ............................................................................................ 235
13 RESET................................................................................................................................................................ 236
13.1 Overview ......................................................................................................................................................... 236
13.2 Reset Source .................................................................................................................................................. 236
13.3 RESET Block Diagram ................................................................................................................................... 236
13.4 RESET Noise Canceller ................................................................................................................................. 237
13.5 Power on RESET ............................................................................................................................................ 237
13.6 External RESETB Input .................................................................................................................................. 240
13.7 Brown Out Detector Processor ....................................................................................................................... 241
13.8 LVI Block Diagram .......................................................................................................................................... 243
13.9 Register Map .................................................................................................................................................. 243
13.10 Reset Operation Register Description ........................................................................................................ 243
13.11 Register Description for Reset Operation ................................................................................................... 244
14 On-chip Debug System(MC96F6432 ONLY) ................................................................................................... 247
14.1 Overview ......................................................................................................................................................... 247
14.1.1 Description ............................................................................................................................................... 247
14.1.2 Feature .................................................................................................................................................... 248
14.2 Two-Pin External Interface.............................................................................................................................. 249
14.2.1 Basic Transmission Packet ..................................................................................................................... 249
14.2.2 Packet Transmission Timing .................................................................................................................... 250
14.2.2.1 Data Transfer ................................................................................................................................................... 250
14.2.2.2 Bit Transfer ...................................................................................................................................................... 250
14.2.2.3 Start and Stop Condition .................................................................................................................................. 251
14.2.2.4 Acknowledge Bit .............................................................................................................................................. 251
14.2.3 Connection of Transmission .................................................................................................................... 252
15 Flash Memory ................................................................................................................................................... 253
15.1 Overview ......................................................................................................................................................... 253
15.1.1 Description ............................................................................................................................................... 253
15.1.2 Flash Program ROM Structure ................................................................................................................ 254
15.1.3 Register Map ........................................................................................................................................... 255
15.1.4 Register Description for Flash Memory Control and Status .................................................................... 255
15.1.5 Register Description for Flash ................................................................................................................. 256
15.1.6 Serial In-System Program (ISP) Mode .................................................................................................... 258
15.1.7 Protection Area (User program mode) .................................................................................................... 258
15.1.8 Erase Mode ............................................................................................................................................. 259
15.1.9 Write Mode .............................................................................................................................................. 260
15.1.10 Protection for Invalid Erase/Write ........................................................................................................ 262
15.1.10.1 Flow of Protection for Invalid Erase/Write ........................................................................................................ 264
15.1.11 Read Mode .......................................................................................................................................... 265
15.1.12 Code Write Protection Mode ................................................................................................................ 265
16 Configure Option .............................................................................................................................................. 266
16.1 Configure Option Control ................................................................................................................................ 266
17 APPENDIX ......................................................................................................................................................... 267
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