SBC-GX1 Technical Manual Award BIOS setup
The following table explains the settings you can choose:
Field Explanation
CPU Internal
Cache
Depending on the CPU/chipset design, enabling this option can
speed up memory access. The default value is ‘enabled’.
Quick Power On
Self Test
If set to ‘Enable’, some of the checks in the Power On Self Test
(POST) are skipped, speeding up the procedure.
Boot Sequence
Determines the sequence in which the computer searches for the
hard disk operation system (e.g. DOS).
Swap Floppy Drive
Users can enable this item so that BIOS will see the hardware
‘Drive A:’ as ‘Drive B:’, and ‘Drive B:’ as ‘Drive A:.
Boot Up Floppy
Seek
Choose whether a test is carried out during the Power On Self
Test (POST), to determine whether the floppy disk drive installed
supports 40 or 80 tracks. 360K drives support 40 tracks while
720K , 1.2M and 1.4M drives support 80 tracks.
Boot Up NumLock
Status
The keypad keys on the keyboard can generate numbers or
arrows, depending on whether the NumLock is turned on or off.
The choice you make here determines the initial setting each time
the computer is turned on.
The default value is ‘On’, which means that the keypad keys will
generate numbers.
Gate A20 Option
This option controls the way the A20 line is used on the SBC-
GX1.The default setting is fast, which is the optimum setting for
this board.
Memory Parity
Check
Enables Parity checking on the main system memory. This option
can only be enabled if the memory module fitted supports the
extra parity bits.
Typematic Rate
Setting, Typematic
Rate (Chars/Sec),
Typematic Delay
(Msec)
Select ‘Enable’ to specify typematic rate settings. You can choose:
• The Typematic Rate. This is the rate at which characters are
generated, i.e. displayed on screen, when a key is pressed
and held down. The options available are: 6, 8, 10, 12, 15,
20, 24 or 30 characters per second.
• The Typematic Delay. This is the time, when holding a key,
between the first and second character being displayed. The
options available are: 250, 500, 750 and 1,000 msec.
continued…
© 2004 Arcom Issue D 32
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