SBC-GX1 Technical Manual Detailed hardware description
258H I/O Write
Bit No. Paged address register 0
0 Address bit A14
1 Address bit A15
2 Address bit A16
3 Address bit A17
4 Address bit A18
5 Address bit A19
6 Address bit A20
7 Address bit A21
259H I/O Write
Bit No. Paged address register 1
0 Address bit A22
1 Address bit A23
2 No function
3 Software flag 1
4 Software flag 2
5 No function
6 FLASH/SRAM selection
0 = Flash pages enabled, 1 = SRAM pages enabled
7 Flash Reset/Power down
0 = device is reset/powered down, 1 = device is enabled
259H I/O Read
Bit No. Paged address register 1
0 Flash busy signal (0 = BUSY)
1 User link 1 LK11 (0 = CLOSED, 1 = OPEN)
2 User link 2 LK12 (0 = CLOSED, 1 = OPEN)
3 Software flag 1
4 Software flag 2
5 No function
6 FLASH/SRAM selection
7 No function
These two I/O registers (258H-259H) are reset to 00h (write) on power up/reset. This
ensures that the Register 1 Bit 7 is 0, i.e. Flash is disabled and write protected.
© 2004 Arcom Issue D 65
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