ARM ARM7TDMI - Page 28

Open Access
Circuit Descriptions
3-12
ARM Development Board (ARM7TDMI Version)
Hardware Reference Guide
ARM DUI 0017C
3.2.7 SRAM ASB Slave
This schematic is shown in A.9 SRAM ASB Slave on page A-10.
The SRAM subsystem comprises:
• an ASB slave controller (U16)
• four 20ns 128KBx8 SRAM devices (U15,U17,U18 and U19)
The controller uses this memory to emulate two logical banks of 8-, 16- or 32-bit wide SRAM.
Although there is one 8-bit wide device connected to each byte lane, the controller simulates
narrow memory systems by inserting the correct number of wait states.
DIP switches
Slow SRAM can also be simulated through the use of DIP switches to control the number of
bus cycles required for a memory access. Two-, three-, four-, and five-cycle memory can be
emulated. DIP switches are also used to determine the memory width.
The controller partitions the memory space into two logical banks of 256KB. The banks are
called bank 0 and bank 1 and each has individual select lines for size and speed.
Switch Name Description Options Default
1 B0CYC0 Bank 0 number of cycles see table below on
2 B0CYC1 Bank 0 number of cycles see table below on
3 B0SIZ0 Bank 0 size (8,16,32-bit) see table below on
4 B0SIZ1 Bank 0 size (8,16,32-bit) see table below off
5 B1CYC0 Bank 1 number of cycles see table below on
6 B1CYC1 Bank 1 number of cycles see table below on
7 B1SIZ0 Bank 1 size (8,16,32-bit) see table below on
8 B1SIZ1 Bank 1 size (8,16,32-bit) see table below off
Table 3-5: DIP switch positions
hrg.book Page 12 Wednesday, July 22, 1998 9:18 AM