The MPS2 and MPS2+ FPGA Prototyping Boards contain the following components and interfaces:
• One Altera Cyclone 5CEA7 FPGA on the MPS2 FPGA Prototyping Board:
— Speed grade C8.
• One Altera Cyclone 5CEA9 FPGA on the MPS2+ FPGA Prototyping Board:
— Speed grade C8.
• External user system memory for Cortex-M processors:
— Two 32-bit 2MB ZBT SSRAM with independent 32-bit memory interfaces.
— One 64-bit 4MB ZBT SSRAM:
◦ Two 32-bit 2MB ZBT SSRAM connected as one 4MB 64-bit memory.
— Two 16-bit 8MB PSRAM to supplement ZBT SSRAM.
• One MCC that supports board configuration at powerup or reset:
— FPGA configuration.
— Clock generator configuration.
— Board configuration.
— Pre-loading of SRAM images.
— Loading of Real Time Clock (RTCC) registers.
— CMSIS-DAP FPGA debug through the USB 2.0 port.
• One microSD card that stores the following:
— FPGA images.
— Software images.
— Board configuration files.
• On‑board clock generators:
— One fixed 25MHz clock for Ethernet MAC/PHY.
— Three programmable system clocks.
— Two crystals for MCC.
• Real Time Clock (RTC) in MCC:
— Powered by 3V lithium coin cell battery.
• I
2
S digital audio output:
• IDC expansion ports:
• Ethernet port.
• UART.
• SPI interface.
• Video output:
— VGA output.
— CLCD output with SPI interface.
• USB 2.0 Full Speed port that supports:
— USB memory access to the microSD card for Drag-and-Drop configuration file editing.
• User switches and user LEDs:
— Two green LEDs and two push buttons that connect to the FPGA.
— Eight green LEDs and one 8-way dip switch that connect to the MCC.
• System LEDs:
— DONE green LED that denotes board powerup and configuration complete.
— PWR green LED that denotes MCC powered up and active.
— HDD green LED that flashes during access to microSD card.
— LINK green LED that denotes Ethernet activity.
— DPLX green LED that denotes Ethernet connection operating in duplex mode.
— 100Mbs green LED that denotes Ethernet connection operating at 10Mbs or 100Mbs.
• Debug and trace interfaces:
— JTAG 20 connector that supports P-JTAG Processor debug and SWD.
— CoreSight 10 connector that supports P-JTAG Processor debug and SWD.
— CoreSight 20 connector that supports P-JTAG Processor debug, SWD, and 4-bit trace.
— MICTOR 38 connector that supports P-JTAG Processor debug, SWD, and 16-bit trace.
— JTAG 14 connector that supports F-JTAG FPGA debug.
— USB 2.0 Full Speed port that supports CMSIS-DAP FPGA debug.
2 Hardware Description
2.1 Overview of the MPS2 and MPS2+ hardware
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