Freescale Semiconductor MC68332 - Background Mode Registers; Returning from BDM; Serial Interface

CENTRAL PROCESSING UNIT MC68332
5-20 USER’S MANUAL
5.10.2.5 Background Mode Registers
BDM processing uses three special purpose registers to keep track of program context
during development. A description of each follows.
5.10.2.5.1 Fault Address Register (FAR)
The FAR contains the address of the faulting bus cycle immediately following a bus or
address error. This address remains available until overwritten by a subsequent bus
cycle. Following a double bus fault, the FAR contains the address of the last bus cycle.
The address of the first fault (if there was one) is not visible to the user.
5.10.2.5.2 Return Program Counter (RPC)
The RPC points to the location where fetching will commence after transition from
background mode to normal mode. This register should be accessed to change the
flow of a program under development. Changing the RPC to an odd value will cause
an address error when normal mode prefetching begins.
5.10.2.5.3 Current Instruction Program Counter (PCC)
The PCC holds a pointer to the first word of the last instruction executed prior to tran-
sition into background mode. Due to instruction pipelining, the instruction pointed to
may not be the instruction which caused the transition. An example is a breakpoint on
a released write. The bus cycle may overlap as many as two subsequent instructions
before stalling the instruction sequencer. A breakpoint asserted during this cycle will
not be acknowledged until the end of the instruction executing at completion of the bus
cycle. PCC will contain $00000001 if BDM is entered via a double bus fault immedi-
ately out of reset.
5.10.2.6 Returning from BDM
BDM is terminated when a resume execution (GO) or call user code (CALL) command
is received. Both GO and CALL flush the instruction pipeline and refetch instructions
from the location pointed to by the RPC.
The return PC and the memory space referred to by the status register SUPV bit reflect
any changes made during BDM. FREEZE is negated prior to initiating the first
prefetch. Upon negation of FREEZE, the serial subsystem is disabled, and the signals
revert to IPIPE
/IFETCH functionality.
5.10.2.7 Serial Interface
Communication with the CPU32 during BDM occurs via a dedicated serial interface,
which shares pins with other development features. Figure 5-9 is a block diagram of
the interface. The BKPT
signal becomes the serial clock (DSCLK); serial input data
(DSI) is received on IFETCH
, and serial output data (DSO) is transmitted on IPIPE.
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