REGISTER SUMMARY MC68332
D-18 USER’S MANUAL
D.4 Queued Serial Module
Table D-4 is the QSM address map. The column labeled “Access” indicates the privi-
lege level at which the CPU must be operating to access the register. A designation of
“S” indicates that supervisor access is required: a designation of “S/U” indicates that
the register can be programmed to the desired privilege level.
Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR.
D.4.1 QSMCR — QSM Configuration Register $YFFC00
QSMCR bits enable stop and freeze modes, and determine the arbitration priority of
QSM interrupt requests.
STOP — Stop Enable
0 = Normal QSM clock operation
1 = QSM clock operation stopped
When STOP is set, the QSM enters low-power stop mode. System clock input to the
module is disabled. While STOP is asserted, only QSMCR reads are guaranteed to be
valid, but writes to QSPI RAM or any register are guaranteed valid. STOP is set during
Table D-4 QSM Address Map
Access Address 15 8 7 0
S $YFFC00 QSM MODULE CONFIGURATION (QSMCR)
S $YFFC02 QSM TEST (QTEST)
S $YFFC04 QSM INTERRUPT LEVEL (QILR) QSM INTERRUPT VECTOR (QIVR)
S/U $YFFC06 NOT USED
S/U $YFFC08 SCI CONTROL 0 (SCCR0)
S/U $YFFC0A SCI CONTROL 1 (SCCR1)
S/U $YFFC0C SCI STATUS (SCSR)
S/U $YFFC0E SCI DATA (SCDR)
S/U $YFFC10 NOT USED
S/U $YFFC12 NOT USED
S/U $YFFC14 NOT USED PQS DATA (PORTQS)
S/U $YFFC16 PQS PIN ASSIGNMENT (PQSPAR) PQS DATA DIRECTION (DDRQS)
S/U $YFFC18 SPI CONTROL 0 (SPCR0)
S/U $YFFC1A SPI CONTROL 1 (SPCR1)
S/U $YFFC1C SPI CONTROL 2 (SPCR2)
S/U $YFFC1E SPI CONTROL 3 (SPCR3) SPI STATUS (SPSR)
S/U $YFFC20–
$YFFCFF
NOT USED
S/U
QUEUE RAM
$YFFD00–
$YFFD1F
RECEIVE RAM (RR[0:F])
S/U
QUEUE RAM
$YFFD20–
$YFFD3F
TRANSMIT RAM (TR[0:F])
S/U
QUEUE RAM
$YFFD40–
$YFFD4F
COMMAND RAM (CR[0:F])
15 14 13 12 11 10 9 8 7 6 5 4 3 0
STOP FRZ1 FRZ0 0 0 0 0 0 SUPV 0 0 0 IARB
RESET:
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
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