Freescale Semiconductor MC68332 - D.2 System Integration Module

MC68332 REGISTER SUMMARY
USER’S MANUAL D-3
D.1.2 SR — Status Register
The status register (SR) contains condition codes, an interrupt priority mask, and three
control bits. The condition codes are contained in the condition code register (CCR),
the lower byte of the SR. (The lower and upper bytes of the status register are also
referred to as the user and system bytes, respectively.) At the user privilege level, only
the CCR is available. At the supervisor level, software can access the full status reg-
ister.
T[1:0] — Trace Enable
00 = No tracing
01 = Trace on change of flow
10 = Trace on instruction execution
11 = Undefined; reserved
S — Supervisor/User State
0 = CPU operates at user privilege level
1 = CPU operates at supervisor privilege level
IP[2:0] — Interrupt Priority Mask
The priority value in this field (0 to 7) is used to mask interrupts.
X — Extend Flag
Used in multiple-precision arithmetic operations. In many instructions it is set to the
same value as the C bit.
N — Negative Flag
Set when the MSB of a result register is set.
Z — Zero Flag
Set when all bits of a result register are zero.
V — Overflow Flag
Set when two's complement overflow occurs as the result of an operation.
C — Carry Flag
Set when a carry or borrow occurs during an arithmetic operation. Also used during
shift and rotate instructions to facilitate multiple word operations.
D.2 System Integration Module
Table D-2 is the SIM address map. The column labeled “Access” indicates the privi-
lege level at which the CPU must be operating to access the register. A designation of
“S” indicates that supervisor access is required. A designation of “S/U” indicates that
the register can be programmed to the desired privilege level.
T[1:0] S 0 0 IP 0 0 0 X N Z V C
RESET:
0 0 1 0 0 1 1 1 0 0 0 U U U U U
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