REGISTER SUMMARY MC68332
D-16 USER’S MANUAL
D.3 Standby RAM Module with TPU Emulation
Table D-3 is the TPURAM address map. TPURAM responds to both program and data
space accesses. The RASP bit in the TRAMMCR determines whether the processor
must be operating at the supervisor privilege level to access the array. TPURAM con-
trol registers are accessible at the supervisor privilege level only.
Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR.
D.3.1 TRAMMCR — TPURAM Module Configuration Register $YFFB00
STOP — Stop Control
0 = TPURAM array operates normally.
1 = TPURAM array enters low-power stop mode.
This bit controls whether the RAM array is in stop mode or normal operation. Reset
state is zero, for normal operation. In stop mode, the array retains its contents, but can-
not be read or written by the CPU.
RASP[1:0] — TPURAM Array Space Field
0 = TPURAM array is accessible from the supervisor or user privilege level.
1 = TPURAM array is accessible from the supervisor privilege level only.
D.3.2 TRAMTST — TPURAM Test Register $YFFB02
TRAMTST is used for factory test of the TPURAM module.
D.3.3 TRAMBAR — TPURAM Base Address and Status Register $YFFB04
ADDR[23:11] — TPURAM Array Base Address
These bits specify address lines ADDR[23:11] of the base address of the TPURAM
array when enabled.
Table D-3 TPURAM Address Map
Access Address 15 8 7 0
S $YFFB00 TPURAM MODULE CONFIGURATION REGISTER (TRAMMCR)
S $YFFB02 TPURAM TEST REGISTER (TRAMTST)
S $YFFB04 TPURAM BASE ADDRESS AND STATUS REGISTER (TRAMBAR)
S $YFFB06 NOT USED
15 14 13 12 11 10 9 8 7 0
STOP 0 0 0 0 0 0 RASP NOT USED
RESET:
0 0 0 0 0 0 0 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
23
ADDR
22
ADDR
21
ADDR
20
ADDR
19
ADDR
18
ADDR
17
ADDR
16
ADDR
15
ADDR
14
ADDR
13
ADDR
12
ADDR
11
NOT USED RAMD
S
RESET:
0 0 0 0 0 0 0 0 0 0 0 0 0 0
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