Freescale Semiconductor MC68332 - Bus Error Signal; Halt Signal; Autovector Signal; Dynamic Bus Sizing

SYSTEM INTEGRATION MODULE MC68332
4-20 USER’S MANUAL
4.4.1.9 Bus Error Signal
The bus error signal (BERR) is asserted when a bus cycle is not properly terminated
by DSACK
or AVEC assertion. BERR can also be asserted at the same time as
DSACK
, provided the appropriate timing requirements are met. Refer to 4.5.5 Bus Ex-
ception Control Cycles for more information.
The internal bus monitor can generate the BERR
signal for internal and internal-to-ex-
ternal transfers. An external bus master must provide its own BERR
generation and
drive the BERR
pin, because the internal BERR monitor has no information about
transfers initiated by an external bus master. Refer to 4.5.6 External Bus Arbitration
for more information.
4.4.1.10 Halt Signal
The halt signa (HALT
) can be asserted by an external device for debugging purposes
to cause single bus cycle operation or (in combination with BERR
) a retry of a bus cy-
cle in error. The HALT
signal affects external bus cycles only, so a program not requir-
ing the use of external bus may continue executing, unaffected by the HALT
signal.
When the MCU completes a bus cycle with the HALT
signal asserted, DATA[15:0] is
placed in the high-impedance state, and bus control signals are driven inactive; the ad-
dress, function code, size, and read/write signals remain in the same state. If HALT
is
still asserted once bus mastership is returned to the MCU, the address, function code,
size, and read/write signals are again driven to their previous states. The MCU does
not service interrupt requests while it is halted. Refer to 4.5.5 Bus Exception Control
Cycles for further information.
4.4.1.11 Autovector Signal
The autovector signal (AVEC
) can be used to terminate external interrupt acknowl-
edge cycles. Assertion of AVEC
causes the CPU32 to generate vector numbers to lo-
cate an interrupt handler routine. If it is continuously asserted, autovectors are
generated for all external interrupt requests. AVEC
is ignored during all other bus cy-
cles. Refer to 4.7 Interrupts for more information. AVEC
for external interrupt re-
quests can also be supplied internally by chip-select logic. Refer to 4.8 Chip Selects
for more information. The autovector function is disabled when there is an external bus
master. Refer to 4.5.6 External Bus Arbitration for more information.
4.4.2 Dynamic Bus Sizing
The MCU dynamically interprets the port size of an addressed device during each bus
cycle, allowing operand transfers to or from 8-bit and 16-bit ports.
During an operand transfer cycle, an external device signals its port size and indicates
completion of the bus cycle to the MCU through the use of the DSACK
inputs, as
shown in Table 4-12. Chip-select logic can generate data and size acknowledge sig-
nals for an external device. Refer to 4.8 Chip Selects for further information.
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Freescale Semiconductor, Inc.
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