Freescale Semiconductor MC68332 - 2.4 Register Mnemonics

NOMENCLATURE MC68332
2-4 USER’S MANUAL
2.4 Register Mnemonics
CFSR[0:3] — Channel Function Select Registers [0:3]
CIER — Channel Interrupt Enable Register
CISR — Channel Interrupt Status Register
CPR[0:1] — Channel Priority Registers [0:1]
CREG — Test Control Register C
CR[0:F] — QSM Command RAM
CSBARBT — Chip-Select Base Address Register Boot ROM
CSBAR[0:10] — Chip-Select Base Address Registers [0:10]
CSORBT — Chip-Select Option Register Boot ROM
CSOR[0:10] — Chip-Select Option Registers [0:10]
CSPAR[0:1] — Chip-Select Pin Assignment Registers [0:1]
DCNR — Decoded Channel Number Register
DDRE — Port E Data Direction Register
DDRF — Port F Data Direction Register
DDRQS — Port QS Data Direction Register
DREG — SIM Test Module Distributed Register
DSCR — Development Support Control Register
DSSR — Development Support Status Register
HSQR[0:1] — Host Sequence Registers [0:1]
HSRR[0:1] — Host Service Request Registers [0:1]
LR — Link Register
PEPAR — Port E Pin Assignment Register
PFPAR — Port F Pin Assignment Register
PICR — Periodic Interrupt Control Register
PITR — Periodic Interrupt Timer Register
PORTC — Port C Data Register
PORTE — Port E Data Register
PORTF — Port F Data Register
PORTQS — Port QS Data Register
PQSPAR — Port QS Pin Assignment Register
QILR — QSM Interrupt Level Register
QIVR — QSM Interrupt Vector Register
QSMCR — QSM Configuration Register
QTEST — QSM Test Register
RR[0:F] — QSM Receive Data RAM
RSR — Reset Status Register
SCCR[0:1] — SCI Control Registers [0:1]
SCDR — SCI Data Register
SCSR — SCI Status Register
SGLR — Service Grant Latch Register
SIMCR — SIM Module Configuration Register
SIMTR — System Integration Test Register
SIMTRE — System Integration Test Register (ECLK)
SPCR[0:3] — QSPI Control Registers [0:3]
SPSR — QSPI Status Register
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