CENTRAL PROCESSING UNIT MC68332
5-22 USER’S MANUAL
Figure 5-10 BDM Serial Data Word
Command and data transfers initiated by the development system should clear bit 16.
The current implementation ignores this bit; however, Freescale reserves the right to
use this bit for future enhancements.
5.10.3 Recommended BDM Connection
In order to provide for use of development tools when an MCU is installed in a system,
Freescale recommends that appropriate signal lines be routed to a male Berg connec-
tor or double-row header installed on the circuit board with the MCU, as shown in the
following figure.
Figure 5-11 BDM Connector Pinout
5.10.4 Deterministic Opcode Tracking
CPU32 function code outputs are augmented by two supplementary signals to monitor
the instruction pipeline. The instruction pipe (I
PIPE) output indicates the start of each
new instruction and each mid-instruction pipeline advance. The instruction fetch (IF-
ETCH) output identifies the bus cycles in which the operand is loaded into the instruc-
tion pipeline. Pipeline flushes are also signaled with I
FETCH. Monitoring these two
signals allows a bus analyzer to synchronize itself to the instruction stream and mon-
itor its activity.
16 15 0
S/C DATA FIELD
⇑
STATUS CONTROL BIT
Table 5-6 CPU Generated Message Encoding
Bit 16 Data Message Type
0 xxxx Valid Data Transfer
0 FFFF Command Complete; Status OK
1 0000 Not Ready with Response; Come Again
1 0001 BERR
Terminated Bus Cycle; Data Invalid
1 FFFF Illegal Command
32 BERG
DS
GND
GND
RESET
V
DD
BERR
BKPT/DSCLK
FREEZE
IFETCH/DSI
IPIPE/DSO
1
3
5
7
9
2
4
6
8
10
Fr
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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