P74x/EN OP/N
(OP) 5-
The output signal is pl(t), it changes between 0 and 1.
Internal overcurrent signals are available per phase and neutral to confirm that the CB failure
algorithm has started to count down.
Internal undercurrent signals are available per phase to confirm that each pole has opened.
To maintain the current criterion active while the signal crosses zero, there is a drop-off timer
associated with the pl(t) signal. The latching duration is variable in order to take all cases into
account:
• Just after the initiation of the CB fail signal, the waveform can include a DC component,
and the time between two successive zero crossings can thus reach one period.
Therefore, the resetting time is equal to the period plus a margin of 3ms (23ms at 50Hz,
20ms at 60Hz).
• For the last 30ms before the end of the stage 2 timer, the DC component should have
disappeared so that the time between two successive zero crossings should be close to
one half-period. Moreover it is important to detect the opening of the circuit breaker
quickly because the end of the back trip timer is near. The drop-off duration is therefore
equal to one half period + 3ms (13ms at 50Hz, 11.3ms at 60Hz).
Tn1
pl (t)
PL
Tn1
pl (t)
PL
P0303ENa
Excitation with zero crossing signal:
Excitation without zero crossing signal:
a
I<
0
&
0
Tbf3
0
Tbf4-
Tbf3
&
Tn
1
Tp
A
E
xte
rna
l sin
gle
pol
e
tri
ppi
ng
s
ig
n
al
fr
o
m
distance protection
Pl(t)
IA
PL
I>
BB confi
rmation
52a status
TpABC
To
gene
ral
t
ripping
Shor
t re
set
time control
by
instan
taneou
s rech
eck at
tBF4 ex
piry
T
o local
r
etrip
>1
&
&
>1
PL
Pl(t)
0
0
0
0
tB
F2-30ms
tFB4-30ms
Pulse Tn1
=(T)+3ms
Pulse Tn1
=(T/2)+3ms
1
7
Interna
l three p
ole
tripping sig
nal fr
om 87BB
Detai
ls of TN1 Cont
rol
P0304ENa
FIGURE 6: CB FAIL ELEMENT LOGIC – PRINCIPLE OF RESET TIME CONTROL
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