Intel® 5000 Series Chipsets Server Board Family Datasheet System BIOS
Revision 1.1
Intel order number D38960-004
43
3.3.10.1.6 Error Period
The error period, or decay rate, defines the rate at which the leaky bucket counter values are
decremented. The decay period is the time period for the leaky bucket count to decay to 0.
Since the frequency of errors is directly related to the size of the FBDIMMs, the BIOS uses the
information in the following table to define the optimal period:
FBDIMM
Size
Decay Period
(Approximate Duration)
512 MB 9 days
1 GB 9 days
2 GB 9 days
4 GB 7 days
3.3.10.1.7 Retry on Error
The Intel
®
5000 MCH will issue a retry on all failures. In mirroring mode, the read transactions
occur on the primary image only. Write transactions are issued to both images. The behavior of
the chipset on encountering an error depends on the transaction in which the error was first
detected.
When the chipset encounters an uncorrectable error on Branch X, it issues a retry on
Branch Y. If the retry succeeds, it corrects the data on both branches and proceeds
normally.
If the retry from the other branch also fails, and if both branches fail on retry, then the
chipset will reset both branches and report a fatal error to the BIOS.
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