Intel Agilex Series User Manual

For PCIe designs including the Configuration via Protocol (CvP), Intel recommends that you use Micron QSPI flash memory.
When using the Micron QSPI flash memory, the boot ROM uses the AS x4 mode to load the initial configuration firmware
faster to meet the PCIe wake-up time for host enumeration.
When using other flash memory types for PCIe designs, the boot ROM reads the firmware using AS x1 mode. Intel
recommends asserting the PERST# signal low for a minimum of 200 ms counting from the device exiting the power-on reset
(POR) state. This ensures the PCIe endpoint enters the link training state prior to the PERST# signal deasserts.
The following block diagram illustrates the components and design flow using the AS configuration scheme.
Figure 37. Components and Design Flow for .jic Programming
Quartus Software flow on PC
Quartus Prime
Programmer
10 pin JTAG header
Intel FPGA Download Cable II
QSPI
Intel FPGA
SDM
Flash
Board
Quartus Prime:
File Programming File Generator
Quartus Prime:
File Start Compile
Quartus Prime:
Tools Programming
Quartus Prime
Programming File
Generator
Quartus Prime
Compilation
USB
SOF
JIC
In addition to AS programming using a .jic, the Programmer supports direct programming of the quad SPI flash using
a .pof as shown in AS Programming Using Intel Quartus Prime or Third-Party Programmer.
3. Intel Agilex Configuration Schemes
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Intel Agilex Series Specifications

General

Architecture	FPGA
AI Tensor Blocks	Yes
Category	FPGA
Family	Agilex
Transceiver Speed	Up to 112 Gbps
Manufacturer	Intel
Series	Agilex
Transceiver Data Rate	Up to 112 Gbps
Memory Support	HBM2E
PCIe Support	PCIe 5.0
Memory	HBM2e
Power Efficiency	Improved over previous generations
Operating Temperature	Commercial, Industrial
Process Technology	10nm