Intel Agilex Series

1. In the IP Catalog locate the Parallel Flash Loader II Intel FPGA IP.
2. On the General tab for What operating mode will be used, select Flash Programming Only.
3. Intel recommends that you turn on the Set flash bus pins to tri-state when not in use.
4. Specify the parameters on the Flash Interface Settings and Flash Programming tabs to match your design.
5.
Compile and generate a .pof for the flash memory device. Ensure that you tri-state all unused I/O pins.
6. To create a second PFL II instantiation for FPGA configuration, on the General tab, for What operating mode will be
used, select FPGA Configuration.
7. Use this Flash Programming Only instance of the PFL II IP to write data to the flash device.
8.
Whenever you must program the flash memory device, program the CPLD with the flash memory device .pof and update
the flash memory device contents.
9.
Reprogram the CPLD with the production design .pof that includes the configuration controller.
Note: By default, all unused pins are set to ground. When programming the configuration flash memory device through
the host JTAG pins, you must tri-state the FPGA configuration pins common to the host and the configuration flash
memory device. You can use the pfl_flash_access_request and pfl_flash_access_granted signals of the
PFL II block to tri-state the correct FPGA configuration pins.
3.1.7.4. Constraining the PFL II IP Core
You can specify many design constraints in Intel Quartus Prime project settings by editing the .sdc files.
3.1.7.4.1. PFL II IP Recommended Design Constraints to FPGA Avalon-ST Pins
Example 1.
Create a pfl_clk clock and a generated AVST_CLK clock
Example below creates a pfl_clk clock running at 50 MHz, supplied by the clk_50m_sysmax input clock.
set pfl_clk_period 20.000
create_clock -name {clk_50m_sysmax} -period $pfl_clk_period [get_ports {clk_50m_sysmax}]
create_generated_clock -name AVST_CLK -source [get_ports {clk_50m_sysmax}] [get_ports {avst_clk}]
3. Intel Agilex Configuration Schemes
683673 | 2021.10.29
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