Intel Agilex Series

Example 2. Set output delay for PFL II IP output pins
Example below sets the output delay for the AvST_DATA and AvST_VALID pins.
set avst_data_tracemax 0.250
set avst_data_tracemin 0.000
set avst_clk_tracemax 0.250
set avst_clk_tracemin 0.000
set fpga_Tsu 2.100
set fpga_Th 0.100
set fpga_out_max_dly [expr $avst_data_tracemax + $fpga_Tsu - $avst_clk_tracemin]
set fpga_out_min_dly [expr $avst_data_tracemin - $fpga_Th - $avst_clk_tracemax]
set_output_delay -add_delay -max -clock [get_clocks {AVST_CLK}] $fpga_out_max_dly [get_ports {avst_d[*] avst_valid}]
set_output_delay -add_delay -min -clock [get_clocks {AVST_CLK}] $fpga_out_min_dly [get_ports {avst_d[*] avst_valid}]
Example 3. Setting a false path
You can set the AVST_READY input pin to a false path since this pin is not synchronous to the AVST_CLK clock. The host must
synchronize the AVST_READY signal to the AVST_CLK signal using a 2-stage register synchronizer.
set_false_path -from [get_ports {avst_ready}] -to *
3.1.7.4.2. PFL II IP Recommended Design Constraints for Using QSPI Flash
Example 4.
Create a FLASH_CLK clock
Example below creates assigns QSPI flash clock pin (flash_dc1_ic0) to the flash clock.
create_generated_clock -name FLASH_CLK -source [get_ports {clk_50m_sysmax}] [get_ports {flash_dc1_io0}]
Example 5. Set output delay for PFL II IP output pins
Example below sets the output delay for the QSPI flash data and chip select pins.
#flash_dc1_io1/3/4/5 = QSPI flash data pins,
#flash_dc1_io2 = QSPI flash chip select pins
set flash_data_tracemax 0.250
set flash_data_tracemin 0.000
set flash_clk_tracemax 0.250
set flash_clk_tracemin 0.000
set flash_Tsu 2.700
set flash_Th 2.000
set flash_out_max_dly [expr $flash_data_tracemax + $flash_Tsu - $flash_clk_tracemin]
3. Intel Agilex Configuration Schemes
683673 | 2021.10.29
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Configuration User Guide
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