Kaypro 2 - 06-18.TIFF

&XI'E SI<N\LS Pm ~ 81-180-0
The examples 0 f correct signals shown here do not represent all 0 f the signals
on the 81-180-n mainboard, since most of the signals will be high-low toggles.
A group 0 f signals taken from a video clock divider (U66) are shown to
illustrate the timing relationships between the various video signals.
The signal measurements were made using a Tektronix ocilloscope, model 2213.
It has a bandwidth of OC-60 MHz, sensitivity of 2mV/em, a sweep delay of 0.1
microseconds to 1 second, and a graticule display measuring 8 x 10 an.
Each square of the representation is the equivalent of one square em. on the
graticule. 'Ihe scope was set fur 2V/div. and .2micro-secs/div. fur all
figures except figure 2, which was set at .5micro-secs/div.
Signal Ml from pin 27 of the CPU (U28) was triggered on. 'Ihis signal is shown
in the top hal f 0 f each display and was channell. Ground fur signals shown
on channel 2 was established at the first graticule line above the 1:x>ttom of
the display.
State 0 f the machine: 'Ihe machine has just 1:x>oted-up on the hard drive.
Figure 1: Pin 6 of U28,
4MHz clock signal;
Figure 2:
Pin
24 of U74,
lMHz clock signal.
Figure 3: Pin
12 of U66,
video, clock divider.
Figure
4: Pin 9 of U66, video,
clock divider.
Figure 5: Pin 8 of U66,
video,
clock divider.
Figure 6: Pin 11 of U66,
video, clock divider.
6-18