Marvell Integrated Controller 88F6281

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88F6281

Hardware Specifications

Page 58 Document Classification: Proprietary Information December 2, 2008, Preliminary

MPP_34 /

GE1[14]

NA MII1_TXEN (out) NA NA

MPP_35 /

GE1[15]

NA MII1_RXERR (in) NA NA

Table 27: Ethernet Ports Pins Multiplexing (Continued)

Pin Name 1xGMII RGMII0+MII1/

MMII1

2xRGMII MII0/MMII0+

RGMII1

Note

When using Gigabit Ethernet signals on MPPs, all relevant Gigabit Ethernet signals

(except those marked as NA) must be implemented. For example, if using MII, and the

chosen PHY does not have an MII_RXERR out signal, the MII_RX_ERR (in) (MPP[35])

must still be configured accordingly and must have a pull-down resistor.

Main Page

Default Chapter1
- Hardware Specifications1
Product Overview3
Features4
- Table of Contents8
Preface15
- About this Document15
- Related Documentation15
- Document Conventions16
Pin and Signal Descriptions17
- Pin Logic18
- Figure 1: 88F6281 Pin Logic Diagram18
- Pin Descriptions19
Pin and Signal Descriptions19
- Table 1: Pin Functions and Assignments Table Key19
- Table 2: Interface Pin Prefix Codes19
- Table 3: Power Pin Assignments21
- Table 4: Miscellaneous Pin Assignments23
- Table 5: DDR SDRAM Interface Pin Assignments24
- Table 6: PCI Express Interface Pin Assignments26
- Table 7: SATA Port Interface Pin Assignment27
- Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments28
- Table 9: Serial Management Interface (SMI) Pin Assignments32
- Table 10: USB 2.0 Interface Pin Assignments33
- Table 11: JTAG Pin Assignment34
- Table 12: RTC Interface Pin Assignments35
- Table 13: NAND Flash Interface Pin Assignment36
- Table 14: MPP Interface Pin Assignment37
- Table 15: Two-Wire Serial Interface (TWSI) Interface Pin Assignment38
- Table 16: UART Port 0/1 Interface Pin Assignment39
- Table 17: Audio (S/PDIF / I 2 S) Interface Signal Assignment40
- Table 18: Serial Peripheral Interface (SPI) Interface Signal Assignment41
- Table 19: Secure Digital Input/Output (SDIO) Interface Signal Assignment42
- Table 20: Time Division Multiplexing (TDM) Interface Signal Assignment43
- Table 21: Transport Stream (TS) Interface Signal Assignment45
- Table 22: Precise Timing Protocol (PTP) Interface Signal Assignment47
- Internal Pull-Up and Pull-Down Pins48
- Table 23: Internal Pull-Up and Pull-Down Pins48
2 Unused Interface Strapping49
Unused Interface Strapping49
- Table 24: Unused Interface Strapping49
88F6281 Pin Map and Pin List50
Pin Multiplexing51
- Multi-Purpose Pins Functional Summary51
4 Pin Multiplexing52
3 88F6281 Pin Map and Pin List52
- Table 25: MPP Functionality52
- Table 26: MPP Function Summary53
- Gigabit Ethernet (Gbe) Pins Multiplexing on MPP57
- Table 27: Ethernet Ports Pins Multiplexing57
- TSMP (TS Multiplexing Pins) on MPP59
- Table 28: TS Port Pin Multiplexing59
5 Clocking60
Clocking60
- Table 29: 88F6281Clocks60
- Table 30: Supported Clock Combinations61
- Spread Spectrum Clock Generator (SSCG)62
6 System Power Up/Down and Reset Settings63
5 Clocking63
System Power Up/Down and Reset Settings63
- Power-Up/Down Sequence Requirements63
- Table 31: I/O and Core Voltages63
- Hardware Reset64
- Figure 2: Power-Up Sequence Example64
- PCI Express Reset66
- Sheeva ™ CPU TAP Controller Reset66
- Pins Sample Configuration66
- Table 32: Reset Configuration67
- Serial ROM Initialization70
- Figure 3: Serial ROM Data Structure70
- Boot Sequence71
- Figure 4: Serial ROM Read Example71
7 JTAG Interface73
JTAG Interface73
- TAP Controller73
- Instruction Register73
- Table 33: Supported JTAG Instructions73
- Bypass Register74
- JTAG Scan Chain74
- ID Register74
- Table 34: IDCODE Register Map74
8 Electrical Specifications (Preliminary)75
Electrical Specifications (Preliminary)75
- Absolute Maximum Ratings75
- Table 35: Absolute Maximum Ratings75
- Recommended Operating Conditions77
- Table 36: Recommended Operating Conditions77
- Thermal Power Dissipation79
- Table 37: Thermal Power Dissipation79
- Current Consumption80
- Table 38: Current Consumption80
- DC Electrical Specifications81
- Table 39: General 3.3V Interface (CMOS) DC Electrical Specifications81
- Table 40: RGMII 1.8V Interface (CMOS) DC Electrical Specifications82
- Table 41: SDRAM DDR2 Interface DC Electrical Specifications83
- Table 42: TWSI Interface 3.3V DC Electrical Specifications84
- Table 43: SPI Interface 3.3V DC Electrical Specifications84
- Table 44: TDM Interface 3.3V DC Electrical Specifications85
- AC Electrical Specifications86
- Table 45: Reference Clock AC Timing Specifications86
- Table 46: SDRAM DDR2 Interface AC Timing Table88
- Table 47: SDRAM DDR2 Interface Address Timing Table89
- Table 48: SDRAM DDR2 Clock Specifications90
- Figure 5: SDRAM DDR2 Interface Test Circuit91
- Figure 6: SDRAM DDR2 Interface Write AC Timing Diagram91
- Figure 7: SDRAM DDR2 Interface Address and Control AC Timing Diagram92
- Figure 8: SDRAM DDR2 Interface Read AC Timing Diagram92
- Table 49: RGMII 10/100/1000 AC Timing Table at 1.8V93
- Table 50: RGMII 10/100 AC Timing Table at 3.3V93
- Figure 9: RGMII Test Circuit94
- Figure 10: RGMII AC Timing Diagram94
- Table 51: GMII AC Timing Table95
- Figure 11: GMII Test Circuit95
- Figure 12: GMII Output AC Timing Diagram96
- Figure 13: GMII Input AC Timing Diagram96
- Table 52: MII/MMII MAC Mode AC Timing Table97
- Figure 14: MII/MMII MAC Mode Test Circuit97
- Figure 15: MII/MMII MAC Mode Output Delay AC Timing Diagram97
- Figure 16: MII/MMII MAC Mode Input AC Timing Diagram98
- Table 53: SMI Master Mode AC Timing Table99
- Figure 17: MDIO Master Mode Test Circuit99
- Figure 18: MDC Master Mode Test Circuit100
- Figure 19: SMI Master Mode Output AC Timing Diagram100
- Figure 20: SMI Master Mode Input AC Timing Diagram100
- Table 54: JTAG Interface AC Timing Table101
- Figure 21: JTAG Interface Test Circuit101
- Figure 22: JTAG Interface Output Delay AC Timing Diagram102
- Figure 23: JTAG Interface Input AC Timing Diagram102
- Table 55: TWSI Master AC Timing Table103
- Table 56: TWSI Slave AC Timing Table103
- Figure 24: TWSI Test Circuit104
- Figure 25: TWSI Output Delay AC Timing Diagram104
- Figure 26: TWSI Input AC Timing Diagram104
- Table 57: S/PDIF AC Timing Table105
- Figure 27: S/PDIF Test Circuit106
- Table 58: Inter-IC Sound (I2S) AC Timing Table107
- Figure 28: Inter-IC Sound (I2S) Test Circuit107
- Figure 29: Inter-IC Sound (I2S) Output Delay AC Timing Diagram108
- Figure 30: Inter-IC Sound (I2S) Input AC Timing Diagram108
- Table 59: TDM Interface AC Timing Table109
- Figure 31: TDM Interface Test Circuit109
- Figure 32: TDM Interface Output Delay AC Timing Diagram110
- Figure 33: TDM Interface Input Delay AC Timing Diagram110
- Table 60: SPI (Master Mode) AC Timing Table111
- Figure 34: SPI (Master Mode) Test Circuit111
- Figure 35: SPI (Master Mode) Output AC Timing Diagram112
- Figure 36: SPI (Master Mode) Input AC Timing Diagram112
- Table 61: SDIO Host in High Speed Mode AC Timing Table113
- Figure 37: Secure Digital Input/Output (SDIO) Test Circuit113
- Figure 38: SDIO Host in High Speed Mode Output AC Timing Diagram114
- Figure 39: SDIO Host in High Speed Mode Input AC Timing Diagram114
- Table 62: Transport Stream Output Interface AC Timing Table115
- Table 63: Transport Stream Input Interface AC Timing Table115
- Figure 40: Transport Stream Interface Test Circuit116
- Figure 41: Transport Stream Output Interface AC Timing Diagram116
- Figure 42: Transport Stream Input Interface AC Timing Diagram117
- Differential Interface Electrical Characteristics118
- Table 64: PCI Express Interface Differential Reference Clock Characteristics118
- Table 65: PCI Express Interface Spread Spectrum Requirements119
- Table 66: PCI Express Interface Driver and Receiver Characteristics120
- Figure 43: PCI Express Interface Test Circuit121
- Table 67: SATA-I Interface Gen1I Mode Driver and Receiver Characteristics123
- Table 68: SATA-II Interface Gen2I Mode Driver and Receiver Characteristics124
- Table 69: USB Low Speed Driver and Receiver Characteristics125
- Table 70: USB Full Speed Driver and Receiver Characteristics126
- Table 71: USB High Speed Driver and Receiver Characteristics127
- Figure 44: Low/Full Speed Data Signal Rise and Fall Time127
- Figure 45: High Speed TX Eye Diagram Pattern Template128
- Figure 46: High Speed RX Eye Diagram Pattern Template128
9 Thermal Data (Preliminary)129
Thermal Data (Preliminary)129
- Table 72: Thermal Data for the 88F6281 in the BGA 19 X 19 MM Package (Preliminary)129
10 Package130
9 Thermal Data (Preliminary)130
Package130
- Figure 47: HSBGA 288-Pin Package and Dimensions130
- Table 73: HSBGA 288-Pin Package Dimensions131
11 Part Order Numbering/Package Marking132
Part Order Numbering/Package Marking132
- Part Order Numbering132
- Table 74: 88F6281 Part Order Options132
- Figure 48: Sample Part Number132
- Package Marking133
- Figure 49: Commercial Package Marking and Pin 1 Location133
Revision History134
- Table 75: Revision History134
A Revision History134

Marvell Integrated Controller 88F6281 - Page 58

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