Marvell Integrated Controller 88F6281 - Page 68

88F6281
Hardware Specifications
Doc. No. MV-S104859-U0 Rev. E Copyright © 2008 Marvell
Page 68 Document Classification: Proprietary Information December 2, 2008, Preliminary
MPP[33],
NF_ALE,
NF_REn,
NF_CLE
CPU_CLK to DDR CLK Ratio
0x0–0x3 = Reserved
0x4 = 3:1
0x5 = Reserved
0x6 = 4:1
0x7 = 4.5:1
0x8 = 5:1
0x9 = 6:1
0xA–0xF = Reserved
NOTE: Internally pulled to 0x4.
The supported combination for CPU_CLK Frequency select, CPU_CLK to DDR CLK ratio,
and CPU_CLK to CPU L2 clock ratio are listed in Table 30, Supported Clock Combinations,
on page 61.
MPP[3], MPP[12],
NF_WEn
CPU_CLK to CPU L2 Clock Ratio
0x0 = Reserved
0x1 = 2:1
0x2 = Reserved
0x3 = 3:1
0x4–0x7 = Reserved
NOTE: Internally pulled to 0x1.
The supported combination for CPU_CLK Frequency select, CPU_CLK to DDR CLK ratio,
and CPU_CLK to CPU L2 clock ratio are listed in Table 30, Supported Clock Combinations,
on page 61.
Table 32: Reset Configuration (Continued)
Pin Configuration Function