Nuvoton NuMicro MS51PC0AE

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MS51

Nov. 28, 2019 Page 209 of 491 Rev 1.00

MS51 32K SERIES TECHNICAL REFERENCE MANUAL

CKDIV – Clock Divider

SFR Address

Reset Value

CKDIV

95H, Page0

0000_0000b

CKDIV[7:0]

R/W

Bit

Name

Description

7:0

CKDIV[7:0]

Clock divider

The system clock frequency FSYS follows the equation below according to CKDIV value.

OSCSYS

F=F

, while CKDIV = 00H, and

CKDIV×2

OSC

SYS

, while CKDIV = 01H to FFH.

System Clock Output 6.2.1.7

The MS51 provides a CLO pin that outputs the system clock. Its frequency is the same as F

SYS

. The

output enable bit is CLOEN (CKCON.1). CLO output stops when device is put in its Power-down mode

because the system clock is turned off. Note that when noise problem or power consumption is

important issue, user had better not enable CLO output.

Main Page

Table of Contents2
General Description10
Features11
Parts Information15
Package Type15
3.2 MS51 Series Selection Gude15
3.3 MS51 Series Selection Code16
Pin Configuration17
MS51 32K Series Multi Function Pin Diagram17
QFN 33-Pin Package Pin Diagram17
Figure 4.1-1 Pin Assignment of LQFP-32 Package17
LQFP 32-Pin Package Pin Diagram18
Figure 4.1-2 Pin Assignment of LQFP-32 Package18
TSSOP 28-Pin Package Pin Diagram19
TSSOP 20-Pin Package Pin Diagram19
Figure 4.1-3 Pin Assignment of TSSOP28 Package19
Figure 4.1-4 Pin Assignment of TSSOP20 Package19
QFN 20-Pin Package Pin Diagram20
Figure 4.1-5 Pin Assignment of QFN20 Package20
MS51 32K Series Pin Description21
Block Diagram25
MS51 32K Series Block Diagram25
Figure 5.1-1 Functional Block Diagram25
Functional Description26
6.1 Memory Organization26
Overview26
Program Memory26
Figure 6.1-1 MS51 Program Memory Map27
Data Flash Memory28
Security Protection Memory (SPROM)28
CONFIG Bytes28
Figure 6.1-2 SPROM Memory Mapping and SPROM Security Mode28
Figure 6.1-3. CONFIG0 any Reset Reloading29
Figure 6.1-4. CONFIG2 Power-On Reset Reloading31
Data Memory34
Figure 6.1-5 Data Memory Map34
Figure 6.1-6 Internal 256 Bytes RAM Addressing35
Special Function Register (SFR)37
Table 6.1-1 Special Function Register Memory Map39
Table 6.1-2 SFR Definitions and Reset Values47
Table 6.1-3 Instructions that Affect Flag Settings133
System Manager201
Clock System201
Figure 6.2-1 Clock System Block Diagram201
Power Management211
Power Monitoring213
Figure 6.2-2 Brown-Out Detection Block Diagram214
Table 6.2-1 BOF Reset Value215
Table 6.2-2 Minimum Brown-Out Detect Pulse Width218
Reset219
Figure 6.2-3 Boot Selecting Diagram224
Timed Access Protection (TA)227
Interrupt System230
Table 6.2-3 Interrupt Vectors230
Table 6.2-4 Interrupt Priority Level Setting236
Table 6.2-5 Characteristics of each Interrupt Source238
Flash Memory Control249
In-Application-Programming (IAP)249
Table 6.3-1 IAP Modes and Command Codes250
In-Circuit-Programming (ICP)265
On-Chip-Debugger (OCD)265
96-Bit Unique Code267
Figure 6.3-1 CONFIG0 any Reset Reloading268
Figure 6.3-2 CONFIG2 Power-On Reset Reloading270
Table 6.4-1 Configuration for Different I/O Modes272
Figure 6.4-1 Quasi-Bidirectional Mode Structure273
Figure 6.4-2 Push-Pull Mode Structure273
Figure 6.4-3 Input-Only Mode Structure274
Figure 6.4-4 Open-Drain Mode Structure274
Figure 6.4-5 Pin Interface Block Diagram275
Figure 6.5-1 Timer/Counters 0 and 1 in Mode 0288
Figure 6.5-2 Timer/Counters 0 and 1 in Mode 1288
Figure 6.5-3 Timer/Counters 0 and 1 in Mode 2288
Figure 6.5-4 Timer/Counter 0 in Mode 3289
Figure 6.5-5 Timer 2 Block Diagram297
Figure 6.5-6 Timer 2 Auto-Reload Mode and Input Capture Module Functional Block Diagram298
Figure 6.5-7 Timer 2 Compare Mode and Input Capture Module Functional Block Diagram299
Figure 6.5-8 Timer 3 Block Diagram314
Table 6.6-1 PWM Pin Define and Enable Control Register319
Figure 6.6-1 PWM0 Block Diagram320
Figure 6.6-2 PWM1/2/3 Block Diagram321
Figure 6.6-3 PWM0 and Fault Brake Output Control Block Diagram322
Figure 6.6-4 PWM1/2/3 Control Block Diagram323
Figure 6.6-5 PWM Edge-Aligned Type Waveform324
Figure 6.6-6 PWM Center-Aligned Type Waveform324
Figure 6.6-7 PWM0 Complementary Mode with Dead-Time Insertion325
Figure 6.6-8 Fault Brake Function Block Diagram326
Figure 6.6-9 PWM Interrupt Type329
Table 6.7-1 Watchdog Timer-Out Interval under Different Pre-Scalars352
Figure 6.7-1 WDT as a Time-Out Reset Timer355
Figure 6.7-2 Watchdog Timer Block Diagram355
Figure 6.8-1 Self Wake-Up Timer Block Diagram359
Figure 6.9-1 Serial Port Mode 0 Timing Diagram363
Figure 6.9-2 Serial Port Mode 1 Timing Diagram364
Figure 6.9-3 Serial Port Mode 2 and 3 Timing Diagram365
Table 6.9-1 Serial Port UART0 Mode / Baudrate Description367
Table 6.9-2 Serial Port UART1 Mode / Baudrate Description367
Figure 6.10-1 SC Controller Block Diagram387
Table 6.10-1 Smart Card or UART Pin Define and Enable Control Register388
Figure 6.10-2 SC Data Character391
Figure 6.10-3 Initial Character TS392
Figure 6.10-4 SC Error Signal392
Figure 6.10-5 Transmit Direction Block Guard Time Operation393
Figure 6.10-6 Receive Direction Block Guard Time Operation393
Figure 6.10-7 Extra Guard Time Operation393
Figure 6.11-1 I 2 C Bus Interconnection408
Figure 6.11-2 I 2 C Bus Protocol409
Figure 6.11-3 START, Repeated START, and STOP Conditions409
Figure 6.11-4 Master Transmits Data to Slave by 7-Bit410
Figure 6.11-5 Master Reads Data from Slave by 7-Bit410
Figure 6.11-6 Data Format of One I C Transfer410
Figure 6.11-7 Acknowledge Bit411
Figure 6.11-8 Arbitration Procedure of Two Masters411
Figure 6.11-9 Control I412
Figure 6.11-10 Flow and Status of Master Transmitter Mode413
Figure 6.11-11 Flow and Status of Master Receiver Mode414
Figure 6.11-12 Flow and Status of Slave Receiver Mode416
Figure 6.11-13 Flow and Status of General Call Mode417
Figure 6.11-14 I 2 C Time-Out Counter422
Figure 6.11-15 Hold Time Extend Enable424
Figure 6.12-1 SPI Block Diagram429
Figure 6.12-2 SPI Multi-Master, Multi-Slave Interconnection430
Figure 6.12-3 SPI Single-Master, Single-Slave Interconnection430
Figure 6.12-4 SPI Clock Formats432
Figure 6.12-5 SPI Clock and Data Format with CPHA = 0433
Figure 6.12-6 SPI Clock and Data Format with CPHA = 1433
Figure 6.12-7 SPI Overrun Waveform435
Figure 6.12-8 SPI Interrupt Request435
Table 6.12-1 Slave Select Pin Configurations438
Figure 6.13-1 12-Bit ADC Block Diagram441
Figure 6.13-2 External Triggering ADC Circuit444
Figure 6.13-3 ADC Result Comparator444
Figure 6.13-4 ADC Continues Mode with DMA445
Figure 7.1-1 Numicro MS51 Power Supply Circuit469
Figure 7.2-1 Numicro470
Figure 7.3-1 Nreset Reset Waveform472
Figure 7.3-2 Low Voltage Reset (LVR) Waveform473
Figure 7.3-3 Power-On Reset (POR) Waveform476
Figure 7.3-4 Low Voltage Reset (LVR) Waveform476
Figure 7.3-5 Brown-Out Detector (BOD) Waveform477
Figure 9.1-1 QFN-33 Package Dimension479
Figure 9.2-1 LQFP-32 Package Dimension480
Figure 9.3-1 TSSOP-28 Package Dimension481
Figure 9.4-1 TSSOP-20 Package Dimension482
Figure 9.5-1 QFN-20 Package Dimension483
Table 10.1-1 List of Abbreviations484
Table 10.1-1 Instruction Set and Addressing Modes485
Table 10.1-2 Instruction Set489

Nuvoton NuMicro MS51PC0AE - Page 209

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