Nuvoton NuMicro MS51PC0AE - Page 221

MS51
Nov. 28, 2019 Page 221 of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
AUXR1 – Auxiliary Register 1
Register
SFR Address
Reset Value
AUXR1
A2H , Page 0
POR: 0000 0000b,
Software reset: 1U00 0000b,
nRESET pin: U100 0000b,
Others: UUU0 0000b
7
6
5
4
3
2
1
0
SWRF
RSTPINF
HardF
SLOW
GF2
UART0PX
0
DPS
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
Bit
Name
Description
6
RSTPINF
External reset flag
When the MCU is reset by the external reset, this bit will be set via hardware. It is recommended
that the flag be cleared via software.
5
HardF
Hard Fault reset flag
Once CPU fetches instruction address over Flash size while EHFI (EIE1.4)=0, MCU will reset
and this bit will be set via hardware. It is recommended that the flag be cleared via software.
Note: If MCU run in OCD debug mode and OCDEN = 0, Hard fault reset will disable. Only
HardF flag be asserted.
Watchdog Timer Reset 6.2.4.5
The WDT is a free running timer with programmable time-out intervals and a dedicated internal clock
source. User can clear the WDT at any time, causing it to restart the counter. When the selected time-
out occurs but no software response taking place for a while, the WDT will reset the system directly
and CPU will begin execution from 0000H.
Once a reset due to WDT occurs, the WDT reset flag WDTRF (WDCON.3) will be set. This bit keeps
unchanged after any reset other than a power-on reset or WDT reset itself. User can clear WDTRF via
software.
WDCON – Watchdog Timer Control
Register
SFR Address
Reset Value
WDCON
AAH, Page 0, TA protected
POR 0000_0111 b
WDT 0000_1UUU b
Others 0000_UUUU b
7
6
5
4
3
2
1
0
WDTR
WDCLR
WDTF
WIDPD
WDTRF
WDPS[2:0]
R/W
R/W
R/W
R/W
R/W
R/W