Nuvoton NuMicro MS51PC0AE - Page 437

MS51
Nov. 28, 2019 Page 437 of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
Bit
Name
Description
1:0
SPR[1:0]
SPI clock rate select
These two bits select four grades of SPI clock divider. The clock rates below are illustrated under F
SYS
= 16 MHz condition.
Fsys = 16 MHz
SPR1
SPR0
Divider
SPI clock rate
0
0
2
8M bit/s
0
1
4
4M bit/s
1
0
8
2M bit/s
1
1
16
1 M bit/s
Fsys = 24 MHz
SPR1
SPR0
Divider
SPI clock rate
0
0
2
12M bit/s
0
1
4
6M bit/s
1
0
8
3M bit/s
1
1
16
1.5M bit/s
SPR[1:0] are valid only under Master mode (MSTR = 1). If under Slave mode, the clock will
automatically synchronize with the external clock on SPICLK pin from Master device up to F
SYS
/2
communication speed.