Nuvoton NuMicro MS51PC0AE - Page 452

MS51
Nov. 28, 2019 Page 452 of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
ADCDLY – ADC Trigger Delay Counter
Register
SFR Address
Reset Value
ADCDLY
E3H, Page 0
0000_0000 b
7
6
5
4
3
2
1
0
ADCDLY[7:0]
R/W
Bit
Name
Description
7:0
ADCDLY[7:0]
ADC external trigger delay counter low byte
This 8-bit field combined with ADCCON2.0 forms a 9-bit counter. This counter inserts a delay
after detecting the external trigger. An A/D converting starts after this period of delay.
External trigger delay time =
ADC
F
ADCDLY
.
Note that this field is valid only when ADCEX (ADCCON1.1) is set. User should not modify
ADCDLY during PWM run time if selecting PWM output as the external ADC trigger source.