MS51
Nov. 28, 2019 Page 474 of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
External Reset and Hard Fault Reset 7.3.1.5
The external reset pin nRESET is an input with a Schmitt trigger. An external reset is accomplished by
holding the nRESET pin low for at least 24 system clock cycles to ensure detection of a valid
hardware reset signal. The reset circuitry then synchronously applies the internal reset signal. Thus,
the reset is a synchronous operation and requires the clock to be running to cause an external reset.
Once the device is in reset condition, it will remain as long as nRESET pin is low. After the nRESET
high is removed, the MCU will exit the reset state and begin code executing from address 0000H. If an
external reset applies while CPU is in Power-down mode, the way to trigger a hardware reset is
slightly different. Since the Power-down mode stops system clock, the reset signal will asynchronously
cause the system clock resuming. After the system clock is stable, MCU will enter the reset state.
There is a RSTPINF (AUXR0.6) flag, which indicates an external reset took place. After the external
reset, this bit will be set as 1 via hardware. RSTPINF will not change after any reset other than a
power-on reset or the external reset itself. This bit can be cleared via software.
Hard Fault reset will occur if CPU fetches instruction address over Flash size, HardF (AUXR0.5) flag
will be set via hardware. HardF will not change after any reset other than a power-on reset or the
external reset itself. This bit can be cleared via software. If MCU run in OCD debug mode and
OCDEN = 0, hard fault reset will be disabled. Only HardF flag be asserted.
AUXR1 – Auxiliary Register 1
POR: 0000 0000b,
Software reset: 1U00 0000b,
nRESET pin: U100 0000b,
Others: UUU0 0000b
External reset flag
When the MCU is reset by the external reset, this bit will be set via hardware. It is recommended
that the flag be cleared via software.
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