Nuvoton NuMicro MS51PC0AE - Page 475

MS51
Nov. 28, 2019 Page 475 of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
Bit
Name
Description
5
HardF
Hard Fault reset flag
Once CPU fetches instruction address over Flash size while EHFI (EIE1.4)=0, MCU will reset
and this bit will be set via hardware. It is recommended that the flag be cleared via software.
Note: If MCU run in OCD debug mode and OCDEN = 0, Hard fault reset will disable. Only
HardF flag be asserted.
Watchdog Timer Reset 7.3.1.6
The WDT is a free running timer with programmable time-out intervals and a dedicated internal clock
source. User can clear the WDT at any time, causing it to restart the counter. When the selected time-
out occurs but no software response taking place for a while, the WDT will reset the system directly
and CPU will begin execution from 0000H.
Once a reset due to WDT occurs, the WDT reset flag WDTRF (WDCON.3) will be set. This bit keeps
unchanged after any reset other than a power-on reset or WDT reset itself. User can clear WDTRF via
software.
WDCON – Watchdog Timer Control
Register
SFR Address
Reset Value
WDCON
AAH, Page 0, TA protected
POR 0000_0111 b
WDT 0000_1UUU b
Others 0000_UUUU b
7
6
5
4
3
2
1
0
WDTR
WDCLR
WDTF
WIDPD
WDTRF
WDPS[2:0]
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Name
Description
3
WDTRF
WDT reset flag
When the CPU is reset by WDT time-out event, this bit will be set via hardware. This flag is
recommended to be cleared via software after reset.
Power-on Reset (POR) 7.3.1.7
The Power-on reset (POR) is used to generate a stable system reset signal and forces the system to
be reset when power-on to avoid unexpected behavior of MCU. When applying the power to MCU, the
POR module will detect the rising voltage and generate reset signal to system until the voltage is
ready for MCU operation. At POR reset, the PORF(SYS_RSTSTS[0]) will be set to 1 to indicate there
is a POR reset event. The PORF(SYS_RSTSTS[0]) bit can be cleared by writing 1 to it. Figure 7.3-3
shows the power-on reset waveform.