Nuvoton NuMicro MS51PC0AE - Page 7

MS51
Nov. 28, 2019 Page 7 of 491 Rev 1.00
MS51 32K SERIES TECHNICAL REFERENCE MANUAL
Figure 6.6-7 PWM0 Complementary Mode with Dead-time Insertion ......................................... 325
Figure 6.6-8 Fault Brake Function Block Diagram ....................................................................... 326
Figure 6.6-9 PWM Interrupt Type ................................................................................................. 329
Figure 6.7-1 WDT as A Time-Out Reset Timer ............................................................................ 355
Figure 6.7-2 Watchdog Timer Block Diagram .............................................................................. 355
Figure 6.8-1 Self Wake-Up Timer Block Diagram ........................................................................ 359
Figure 6.9-1 Serial Port Mode 0 Timing Diagram ........................................................................ 363
Figure 6.9-2 Serial Port Mode 1 Timing Diagram ........................................................................ 364
Figure 6.9-3 Serial Port Mode 2 and 3 Timing Diagram .............................................................. 365
Figure 6.10-1 SC Controller Block Diagram ................................................................................. 387
Figure 6.10-2 SC Data Character ............................................................................................... 391
Figure 6.10-3 Initial Character TS .............................................................................................. 392
Figure 6.10-4 SC Error Signal ..................................................................................................... 392
Figure 6.10-5 Transmit Direction Block Guard Time Operation .................................................. 393
Figure 6.10-6 Receive Direction Block Guard Time Operation .................................................... 393
Figure 6.10-7 Extra Guard Time Operation ................................................................................. 393
Figure 6.11-1 I
2
C Bus Interconnection ......................................................................................... 408
Figure 6.11-2 I
2
C Bus Protocol .................................................................................................... 409
Figure 6.11-3 START, Repeated START, and STOP Conditions ............................................... 409
Figure 6.11-4 Master Transmits Data to Slave by 7-bit ............................................................... 410
Figure 6.11-5 Master Reads Data from Slave by 7-bit ................................................................. 410
Figure 6.11-6 Data Format of One I
2
C Transfer........................................................................... 410
Figure 6.11-7 Acknowledge Bit .................................................................................................... 411
Figure 6.11-8 Arbitration Procedure of Two Masters ................................................................... 411
Figure 6.11-9 Control I
2
C Bus according to the Current I
2
C Status ............................................. 412
Figure 6.11-10 Flow and Status of Master Transmitter Mode ..................................................... 413
Figure 6.11-11 Flow and Status of Master Receiver Mode ......................................................... 414
Figure 6.11-12 Flow and Status of Slave Receiver Mode............................................................ 416
Figure 6.11-13 Flow and Status of General Call Mode ................................................................ 417
Figure 6.11-14 I
2
C Time-Out Counter .......................................................................................... 422
Figure 6.11-15 Hold Time extend enable ..................................................................................... 424
Figure 6.12-1 SPI Block Diagram ................................................................................................. 429
Figure 6.12-2 SPI Multi-Master, Multi-Slave Interconnection ...................................................... 430
Figure 6.12-3 SPI Single-Master, Single-Slave Interconnection .................................................. 430
Figure 6.12-4 SPI Clock Formats ................................................................................................. 432
Figure 6.12-5 SPI Clock and Data Format with CPHA = 0 .......................................................... 433
Figure 6.12-6 SPI Clock and Data Format with CPHA = 1 .......................................................... 433