NXP Semiconductors MPC5777M - Page 155

Document revision history
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 155
3 3/2014
Electrical characteristics—Oscillator and FMPLL
Section 3.12, Oscillator and FMPLL
• Updated text to reflect that there is one FMPLL on the chip.
Table 22 (PLL1 electrical characteristics)
•f
PLL1PHI
parameter, changed Max freq from “200” MHz to “600” MHz.
• First footnote, changed “FXOSC” to “XOSC”.
Table 23 (External Oscillator electrical specifications):
• Added footnote to both V
IHEXT
and V
ILEXT
parameter column “Applies to an external
clock input and not to crystal mode”.
• Added footnote to V
ILEXT
parameter column “This parameter is guaranteed by design
rather than 100% tested.”
•V
ILEXT
parameter, changed “External Reference” to “External Clock Input”.
• Combined C
S_XTAL
and C
S_EXTAL
parameters into one specification C
S_xtal
, updated
Min and Max values and removed the “BG292” condition.
Table 24 (Selectable load capacitance):
• Removed last 16 rows “10000” to “11111”.
• Changed footnote 2 from “Values in this table do not include 8 pF routing and ESD
structure on die and package trace capacitance.” to “Values in this table do not include
the die and package capacitances given by Cs_xtal/Cs_extal in Table 23 (External
Oscillator electrical specifications).”
• Table 25 (Internal RC Oscillator electrical specifications): f
var_SW
parameter added
footnote “IRC software trimmed accuracy is performed either with the CMU_0 clock
monitor, using the XOSC as a reference or through the CCCU (CAN clock control Unit),
extracting reference clock from CAN master clock. Software trim must be repeated as
the device operating temperature varies in order to maintain the specified accuracy.”
Electrical characteristics—ADC specifications
Table 36 (ADC pin specification
,
):
•I
LK_INUD
, I
LK_INUSD
, I
LK_INREF
, I
LK_INOUT
: Removed footnote “Leakage current is a
parameter potentially showing variation with process maturity. This table is based on
current process model, and will be validated when preliminary silicon data of ADC
modules and I/O module is available.”
• Parameter I
LK_INOUT
description column, changed “MEDIUM” output buffer with
“GPIO” output buffer.
Table 27 (SARn ADC electrical specification):
• Added new condition for “V
PRECH
” - “V
PRECH
= V
DD_HV_ADR
/2 T
J
<150°C
CTRn[PRECHG] > 2”
•I
ADCREFL
specification: added V
DD_HV_ADR_S
<= 5.5 V to all modes in condition
column.
•D
NL
, “Differential non-linearity” parameter, conditions column, replaced “—” with
“V
DD_HV_ADV > 4V, VDD_HV_ADR_S > 4V”.
•I
NL
: Conditions column, first row, removed T
J
< 150C and added 4.0V <
V
DD_HV_ADV_S
< 5.5V. Conditions column, second row, removed T
J
< 150C and added
V
DD_HV_ADV_S
=2V.
Table 76. Revision history (continued)
Revision Date Description of changes