7 High-speed Counters
7-20
CJ2M CPU Unit Pulse I/O Module User’s Manual
z Reading the High-speed Counter Status with a PRV(881) Instruction
If a Gate Bit (A531.08 to A531.11) of a high-speed counter 0 to 3 is turned ON, the high-speed
counter will not count even if pulse inputs are received and the counter PV will be maintained at its
current value. When the Gate Bit of the high-speed counter is turned OFF again, the high-speed
counter will resume counting and the counter PV will be refreshed.
Precautions for Correct UsePrecautions for Correct Use
The Gate Bit will be disabled if the high-speed counter reset method is set to a phase-Z signal +
software reset and the Reset Bit is ON (i.e., waiting for the phase-Z input to reset the counter
PV.)
Additional Information
Even if a Gate Bit is ON, the INI(880) instruction can be used to change the PV or execute a soft-
ware reset.
Reading the Value from the Ladder Program
7-2-8 Temporarily Stopping Input Signal Counting (Gate Function)
Execution condition
@PRV
#0010
#0001
D100
C: Control data for reading status
P: Port specifier, Example: High-speed counter input 0
D: First destination word (for status)
Comparison operation
OFF: Stopped.
ON: Being executed.
PV overflow/underflow
OFF: Normal
ON: Overflow or underflow
Count direction
OFF: Decrementing
ON: Incrementing
015
D100
000 0 0 0 0 0 00000
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