621
Auxiliary Area Allocations by Function Appendix C
Built-in Analog Inputs (XA CPU Units)
Built-in Outputs
Pulse Outputs 0 to 3
Name Description Read/Write Updated
High-speed Counter PV Contains the PV of the high-speed counter. Read-only • Cleared when power is turned ON.
• Cleared when operation starts.
• Updated each cycle during oversee-
ing process.
• Updated when PRV(881) instruction
is executed for the corresponding
counter.
High-speed
Counter Range
Comparison
Condition Met
Flags
Range 1 These flags indicate whether the PV is within the
specified ranges when the high-speed counter is
being operated in range-comparison mode.
OFF: PV not in range
ON: PV in range
Read-only • Cleared when power is turned ON.
• Cleared when operation starts.
• Cleared when range comparison
table is registered.
• Updated each cycle during oversee-
ing process.
• Updated when PRV(881) instruction
is executed to read range compari-
son results.
Range 2
Range 3
Range 4
Range 5
Range 6
Range 7
Range 8
High-speed Counter Com-
parison In-progress Flag
This flag indicates whether a comparison operation
is being executed for the high-speed counter.
OFF: Stopped.
ON: Being executed.
Read-only • Cleared when power is turned ON.
• Cleared when operation starts.
• Updated when comparison operation
starts or stops.
High-speed Counter Over-
flow/Underflow Flag
This flag indicates when an overflow or underflow
has occurred in the high-speed counter PV. (Used
with the linear mode counting range only.)
OFF: Normal
ON: Overflow or underflow
Read-only • Cleared when power is turned ON.
• Cleared when operation starts.
• Cleared when the PV is changed.
• Updated when an overflow or under-
flow occurs.
High-speed Counter
Count Direction
This flag indicates whether the high-speed counter
is currently being incremented or decremented. The
counter PV for the current cycle is compared with
the PLC in last cycle to determine the direction.
OFF: Decrementing
ON: Incrementing
Read-only • Setting used for high-speed counter,
valid during counter operation.
High-speed Counter
Reset Bit
When the reset method is set to Phase-Z signal +
Software reset, the corresponding high-speed
counter's PV will be reset if the phase-Z signal is
received while this bit is ON.
When the reset method is set to a software reset,
the corresponding high-speed counter's PV will be
reset in the cycle when this bit goes ON.
Read/Write • Cleared when power is turned ON.
High-speed Counter Gate
Bit
When a counter's Gate Bit is ON, the counter's PV
will not be changed even if pulse inputs are received
for the counter.
When the bit is turned OFF again, counting will
restart and the high-speed counter's PV will be
updated.
When the reset method is set to Phase-Z signal +
Software reset, the Gate Bit is disabled while the
corresponding Reset Bit is ON.
Read/Write • Cleared when power is turned ON.
Name Address Description Read/Write Updated
Built-in Analog Input
Error Details
A434.00 to
A434.03
ON when an error occurs in a built-in analog input.
A434.00: Analog Input 0 Open-circuit Error Flag
A434.01: Analog Input 1 Open-circuit Error Flag
A434.02: Analog Input 2 Open-circuit Error Flag
A434.03: Analog Input 3 Open-circuit Error Flag
Read-only When open-circuit is
detected
Analog Initialization
Completed Flag
A434.04 ON while the built-in analog I/O is being initialized. Read-only When initialization is
completed
Item Pulse output
0
Pulse output
1
Pulse output
2
Pulse output
3
Pulse Output PV Leftmost 4 digits A277 A279 A323 A325
Rightmost 4 digits A276 A278 A322 A324
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