Commissioning
S7-300 Programmable Controller Hardware and Installation
A5E00105492-01
8-33
CALL SFC 14 //receive data
LADDR:=W#16#D from DP master
RET_VAL:=MW 20
RECORD:=P#M30.0 byte 20
L MB 30 // processing
received data
L MB 7 processing
+I
T MW 100
Working with intermediate memory
Note the following rules when working with intermediate memory:
• Assignment of address areas:
– Input data of DP slaves are always output data of the DP master
– Output data of DP slaves are always input data of the DP master
• The user can define these addresses. In the user program, access data with
load/transfer instructions or with SFC 14 and 15. You can also specify
addresses from the input/output process image (refer to Chapter Addressing,
User-defined Addressing of Modules).
• The lowest address of specific address areas is their respective area start
address.
• The length, unit and consistency of the address areas for DP master and DP
slave must be identical.
Note
Assign intermediate memory addresses taken from the DP address area of
CPU 31x-2 DP/31xC-2 DP.
Addresses assigned to intermediate memory cannot be assigned again to I/O
modules of CPU 31x-2 DP/31xC-2 DP. When using consistent data areas in
intermediate memory, note the section on Consistent Data in Chapter
Addressing.
S5 DP Master
When exchanging consistent data with IM 308-C operating as DP master and
CPU 31x-2 DP/31xC-2 DP as DP slave, note that:
You must program FB192 in IM 308-C to enable exchange of consistent data
between a DP master and the DP slave. FB192 reads or outputs CPU 31x-
2 DP/31xC-2 DP data only in a single continuous block.
S5-95 as DP Master
Bus parameters of an AG S5-95 operated as DP master must also be set in
CPU 31x-2 DP/31xC-2 DP operating as DP slave.
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