ST STM32F103 series Reference Manual

Revision history RM0008
1119/1128 DocID13902 Rev 15
02-Jun-
2014
15
(continued)
FSMC:
Updated Figure 185: FSMC block diagram.
Updated Table 109 to Table 128.
Replaced all occurrences of DATALAT by DATLAT in the whole section. Updated
Section 21.1: FSMC main features. Replace SRAM/CRAM by SRAM/PSRAM in the
whole section.
Updated Section 21.5.3: General timing rules/Signals synchronization.
– Updated Section 21.5.4: NOR Flash/PSRAM controller asynchronous transactions
– Modified step b) in Section 21.3.1: Supported memories and transactions.
– Moved note from Figure 188: Mode1 write accesses to Figure 187: Mode1 read
accesses.
– Moved note from Figure 190: ModeA write accesses to Figure 189: ModeA read
accesses. Updated Section : WAIT management in asynchronous accesses and
Figure 199: Asynchronous wait during a read access.
– Modified differences between Mode B and mode 1 in Section : Mode 2/B - NOR Flash.
– Modified differences between Mode C and mode 1 in Section : Mode C - NOR Flash -
OE toggling.
– Modified differences between Mode D and mode 1 in Section : Mode D -
asynchronous access with extended address.
– Updated NWAIT signal in Figure 199: Asynchronous wait during a read access,
Figure 200: Asynchronous wait during a write access, Figure 201: Wait configurations,
Figure 202: Synchronous multiplexed read mode - NOR, PSRAM (CRAM), and
Figure 203: Synchronous multiplexed write mode - PSRAM (CRAM).
Updated case of synchronous accesses in Section 21.5: NOR Flash/PSRAM controller.
Added register access in Section 21.5.6: NOR/PSRAM control registers and
Section 21.6.8: NAND Flash/PC Card control registers.
Updated step3 of Section 21.6.4: NAND Flash operations, updated Figure 205: Access
to non ‘CE don’t care’ NAND-Flash and note below.
Updated Section 21.6.6: Computation of the error correction code (ECC) in NAND Flash
memory.
Updated access to I/O Space in Section 21.6.7: PC Card/CompactFlash operations.
Updated Table 132: 16-bit PC Card.
Changed bits 16 to 19 to BUSTURN in Section : SRAM/NOR-Flash write timing registers
1..4 (FSMC_BWTR1..4). Updated BUSTURN bit definition in Section : SRAM/NOR-
Flash chip-select timing registers 1..4 (FSMC_BTR1..4). Updated
Section : SRAM/NOR-
Flash chip-select control registers 1..4 (FSMC_BCR1..4).
Updated definition of PWID in Section : PC Card/NAND Flash control registers 2..4
(FSMC_PCR2..4).
Table 235. Document revision history (continued)
Date Revision Changes

ST STM32F103 series Specifications

General

Brand	ST
Model	STM32F103 series
Category	Microcontrollers
Language	English