ST STM32F103 series

DocID13902 Rev 15 298/1128
RM0008 Advanced-control timers (TIM1&TIM8)
359
Figure 57. Counter timing diagram, internal clock divided by 4
Figure 58. Counter timing diagram, internal clock divided by N
Figure 59. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded)
CK_PSC
0000 0001
CNT_EN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
0035
0036
Counter overflow
Update event (UEV)
Timer clock = CK_CNT
Counter register
00
1F
20
Update interrupt flag (UIF)
Counter overflow
Update event (UEV)
CK_PSC
CK_PSC
00
CEN
Timer clock = CK_CNT
Counter register
Update interrupt flag (UIF)
Counter overflow
Update event (UEV)
01 02 03 04 05 06 0732 33 34 35 3631
Auto-reload register
FF 36
Write a new value in TIMx_ARR