Flexible static memory controller (FSMC) RM0008
521/1128 DocID13902 Rev 15
Muxed mode - multiplexed asynchronous access to NOR Flash memory
Figure 197. Multiplexed read accesses
1. The bus turnaround delay (BUSTURN + 1) and the delay between side-by-side transactions overlap, so
BUSTURN ≤ 5 has not impact.
Table 122. FSMC_BWTRx bit fields
Bit No. Bit name Value to set
31:30 Reserved 0x0
29-28 ACCMOD 0x3
27-24 DATLAT 0x0
23-20 CLKDIV 0x0
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST
Duration of the second access phase (DATAST+3 HCLK cycles) for
write accesses. This value cannot be 0 (minimum is 1)
7-4 ADDHLD
Duration of the middle phase of the write access (ADDHLD+1 HCLK
cycles)
3-0 ADDSET
Duration of the first access phase (ADDSET+1 HCLK cycles) for
write accesses.
A[25:16]
NOE
(ADDSET +1) (DATAST + 1)
Memory transaction
Data strobe
NEx
AD[15:0]
HCLK cycles HCLK cycles
NWE
NADV
data driven
by memory
ai14728c
High
(ADDHLD + 1)
HCLK cycles
Lower address
(BUSTURN + 1)
(1)
HCLK cycles
2 HCLK
cycles
Data sampled
1HCLK cycle
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