Memory and bus architecture RM0008
55/1128 DocID13902 Rev 15
3.3.3 Embedded Flash memory
The high-performance Flash memory module has the following key features:
• For XL-density devices: density of up to 1 Mbyte with dual bank architecture for read-
while-write (RWW) capability:
– bank 1: fixed size of 512 Kbytes
– bank 2: up to 512 Kbytes
• For other devices: density of up to 512 Kbytes
• Memory organization: the Flash memory is organized as a main block and an
information block:
– Main memory block of size:
up to 128 Kbytes × 64 bits divided into 512 pages of 2 Kbytes each (see Table 8)
for XL-density devices
up to 4 Kb × 64 bits divided into 32 pages of 1 Kbyte each for low-density devices
(see Table 4)
up to 16 Kb × 64 bits divided into 128 pages of 1 Kbyte each for medium-density
devices (see Table 5)
up to 64 Kb × 64 bits divided into 256 pages of 2 Kbytes each (see Table 6) for
high-density devices
up to 32 Kbit × 64 bits divided into 128 pages of 2 Kbytes each (see Table 7) for
connectivity line devices
– Information block of size:
770 × 64 bits for XL-density devices (see Table 8)
2360 × 64 bits for connectivity line devices (see Table 7)
258 × 64 bits for other devices (see Table 4, Table 5 and Table 6)
The Flash memory interface (FLITF) features:
• Read interface with prefetch buffer (2x64-bit words)
• Option byte Loader
• Flash Program / Erase operation
• Read / Write protection
Table 4. Flash module organization (low-density devices)
Block Name Base addresses Size (bytes)
Main memory
Page 0 0x0800 0000 - 0x0800 03FF 1 Kbyte
Page 1 0x0800 0400 - 0x0800 07FF 1 Kbyte
Page 2 0x0800 0800 - 0x0800 0BFF 1 Kbyte
Page 3 0x0800 0C00 - 0x0800 0FFF 1 Kbyte
Page 4 0x0800 1000 - 0x0800 13FF 1 Kbyte
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Page 31 0x0800 7C00 - 0x0800 7FFF 1 Kbyte
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