Analog-to-digital converter (ADC) RM0008
215/1128 DocID13902 Rev 15
11.2 ADC main features
• 12-bit resolution
• Interrupt generation at End of Conversion, End of Injected conversion and Analog
watchdog event
• Single and continuous conversion modes
• Scan mode for automatic conversion of channel 0 to channel ‘n’
• Self-calibration
• Data alignment with in-built data coherency
• Channel by channel programmable sampling time
• External trigger option for both regular and injected conversion
• Discontinuous mode
• Dual mode (on devices with 2 ADCs or more)
• ADC conversion time:
– STM32F103xx performance line devices: 1 µs at 56 MHz (1.17 µs at 72 MHz)
– STM32F101xx access line devices: 1 µs at 28 MHz (1.55 µs at 36 MHz)
– STM32F102xx USB access line devices: 1.2 µs at 48 MHz
– STM32F105xx and STM32F107xx devices: 1 µs at 56 MHz (1.17 µs at 72 MHz)
• ADC supply requirement: 2.4 V to 3.6 V
• ADC input range: V
REF-
≤ V
IN
≤ V
REF+
• DMA request generation during regular channel conversion
The block diagram of the ADC is shown in Figure 22.
Note: V
REF-
,if available (depending on package), must be tied to V
SSA
.
11.3 ADC functional description
Figure 22 shows a single ADC block diagramand Table 65 gives the ADC pin description.
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