ST STM32F103 series Reference Manual

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RM0008 Flexible static memory controller (FSMC)
555
1 MUXEN 0x0
0 MBKEN 0x1
Table 118. FSMC_BTRx bit fields
Bit
number
Bit name Value to set
31:30 Reserved 0x0
29-28 ACCMOD 0x2
27-24 DATLAT 0x0
23-20 CLKDIV 0x0
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST
Duration of the second access phase (DATAST+3 HCLK cycles) for
read accesses.
This value cannot be 0 (minimum is 1).
7-4 ADDHLD Don’t care
3-0 ADDSET
Duration of the first access phase (ADDSET+1 HCLK cycles) for
read accesses.
Table 119. FSMC_BWTRx bit fields
Bit
number
Bit name Value to set
31:30 Reserved 0x0
29-28 ACCMOD 0x2
27-24 DATLAT Don’t care
23-20 CLKDIV Don’t care
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST
Duration of the second access phase (DATAST+1 HCLK cycles for
write accesses, DATAST+3 HCLK cycles for write accesses).
This value cannot be 0 (minimum is 1).
7-4 ADDHLD Don’t care
3-0 ADDSET
Duration of the first access phase (ADDSET+1 HCLK cycles) for
write accesses.
Table 117. FSMC_BCRx bit fields (continued)
Bit No. Bit name Value to set

ST STM32F103 series Specifications

General

Brand	ST
Model	STM32F103 series
Category	Microcontrollers
Language	English