DocID13902 Rev 15 528/1128
RM0008 Flexible static memory controller (FSMC)
555
Figure 202. Synchronous multiplexed read mode - NOR, PSRAM (CRAM)
1. Byte lane outputs BL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access,
they are held low.
2. NWAIT polarity is set to 0.
!DDR;= DATA DATA
ADDR;=
-EMORYTRANSACTIONBURSTOFHALFWORDS
(#,+
#,+
!;=
.%X
./%
.7%
(IGH
.!$6
.7!)4
7!)4#&'
!$;=
CLOCK
CYCLE
CLOCK
CYCLE
$!4,!4
INSERTEDWAITSTATE
$ATASTROBES
AID
#,+CYCLES
DATA DATA
$ATASTROBES
Table 125. FSMC_BCRx bit fields
Bit No. Bit name Value to set
31-20 Reserved 0x000
19 CBURSTRW No effect on synchronous read
18-16 Reserved 0x0
15 ASCYCWAIT 0x0
14 EXTMOD 0x0
13 WAITEN Set to 1 if the memory supports this feature, otherwise keep at 0.
12 WREN no effect on synchronous read
11 WAITCFG to be set according to memory
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