DocID13902 Rev 15 70/1128
RM0008 Power control (PWR)
80
5.1.3 Voltage regulator
The voltage regulator is always enabled after Reset. It works in three different modes
depending on the application modes.
• In Run mode, the regulator supplies full power to the 1.8 V domain (core, memories
and digital peripherals).
• In Stop mode the regulator supplies low-power to the 1.8 V domain, preserving
contents of registers and SRAM
• In Standby Mode, the regulator is powered off. The contents of the registers and SRAM
are lost except for the Standby circuitry and the Backup Domain.
5.2 Power supply supervisor
5.2.1 Power on reset (POR)/power down reset (PDR)
The device has an integrated POR/PDR circuitry that allows proper operation starting
from/down to 2 V.
The device remains in Reset mode when V
DD
/V
DDA
is below a specified threshold,
V
POR/PDR
, without the need for an external reset circuit. For more details concerning the
power on/power down reset threshold, refer to the electrical characteristics of the datasheet.
Figure 5. Power on reset/power down reset waveform
5.2.2 Programmable voltage detector (PVD)
You can use the PVD to monitor the V
DD
/V
DDA
power supply by comparing it to a threshold
selected by the PLS[2:0] bits in the Power control register (PWR_CR).
The PVD is enabled by setting the PVDE bit.
A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate if
V
DD
/V
DDA
is higher or lower than the PVD threshold. This event is internally connected to
the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The
V
DD
/V
DDA
Reset
40 mV
hysteresis
POR
PDR
Temporization
t
RSTTEMPO
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