DocID13902 Rev 15 538/1128
RM0008 Flexible static memory controller (FSMC)
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21.6 NAND Flash/PC Card controller
The FSMC generates the appropriate signal timings to drive the following types of device:
• NAND Flash
–8-bit
– 16-bit
• 16-bit PC Card compatible devices
The NAND/PC Card controller can control three external banks. Bank 2 and bank 3 support
NAND Flash devices. Bank 4 supports PC Card devices.
Each bank is configured by means of dedicated registers (Section 21.6.8). The
programmable memory parameters include access timings (shown in Table 129) and ECC
configuration.
Bits 15:8 DATAST: Data-phase duration.
These bits are written by software to define the duration of the data phase (refer to Figure 187 to
Figure 198), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:
0000 0000: Reserved
0000 0001: DATAST phase duration = 2 × HCLK clock cycles
0000 0010: DATAST phase duration = 3 × HCLK clock cycles
...
1111 1111: DATAST phase duration = 16 × HCLK clock cycles (default value after reset)
Note: In synchronous accesses, this value is don't care.
Bits 7:4 ADDHLD: Address-hold phase duration.
These bits are written by software to define the duration of the address hold phase (refer to
Figure 196 to Figure 198), used in asynchronous multiplexed accesses:
0000: Reserved
0001: ADDHLD phase duration = 2 × HCLK clock cycle
0010: ADDHLD phase duration = 3 × HCLK clock cycle
...
1111: ADDHLD phase duration = 16 × HCLK clock cycles (default value after reset)
Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always
1 Flash clock period duration.
Bits 3:0 ADDSET: Address setup phase duration.
These bits are written by software to define the duration of the address setup phase in HCLK
cycles (refer to Figure 196 to Figure 198), used in asynchronous accessed:
0000: ADDSET phase duration = 1 × HCLK clock cycle
...
1111: ADDSET phase duration = 16 × HCLK clock cycles (default value after reset)
Note: In synchronous NOR Flash accesses, this value is don’t care.
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