Power control (PWR) RM0008
75/1128 DocID13902 Rev 15
Section 19.3: IWDG functional description in Section 19: Independent watchdog
(IWDG).
• real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain
control register (RCC_BDCR)
• Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
• External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
Backup domain control register (RCC_BDCR).
The ADC or DAC can also consume power during the Stop mode, unless they are disabled
before entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit
in the DAC_CR register must both be written to 0.
Note: If the application needs to disable the external clock before entering Stop mode, the HSEON
bit must first be disabled and the system clock switched to HSI. Otherwise, if the HSEON bit
remains enabled and the external clock (external oscillator) is removed when entering Stop
mode, the clock security system (CSS) feature must be enabled to detect any external
oscillator failure and avoid a malfunction behavior when entering stop mode.
Exiting Stop mode
Refer to Table 1 4 for more details on how to exit Stop mode.
When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is
selected as system clock.
When the voltage regulator operates in low-power mode, an additional startup delay is
incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop
mode, the consumption is higher although the startup time is reduced.
Table 14. Stop mode
Stop mode Description
Mode entry
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– Set SLEEPDEEP bit in Cortex
®
-M3 System Control register
– Clear PDDS bit in Power Control register (PWR_CR)
– Select the voltage regulator mode by configuring LPDS bit in PWR_CR
Note: To enter Stop mode, all EXTI Line pending bits (in Pending register
(EXTI_PR)), all peripheral interrupt pending bits, and RTC Alarm flag must
be reset. Otherwise, the Stop mode entry procedure is ignored and
program execution continues.
Mode exit
If WFI was used for entry:
Any EXTI Line configured in Interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). Refer to Section 10.1.2:
Interrupt and exception vectors on page 197.
If WFE was used for entry:
Any EXTI Line configured in event mode. Refer to Section 10.2.3:
Wakeup event management on page 206
Wakeup latency HSI RC wakeup time + regulator wakeup time from Low-power mode
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