ST STM32F31xx

General-purpose timers (TIM)
UM1581
448/584
DocID023800 Rev 1
 TIM slave mode control register, Address offset: 0x08
 __IO uint32_t TIM_TypeDef::DIER
 TIM DMA/interrupt enable register, Address offset: 0x0C
 __IO uint32_t TIM_TypeDef::SR
 TIM status register, Address offset: 0x10
 __IO uint32_t TIM_TypeDef::EGR
 TIM event generation register, Address offset: 0x14
 __IO uint32_t TIM_TypeDef::CCMR1
 TIM capture/compare mode register 1, Address offset: 0x18
 __IO uint32_t TIM_TypeDef::CCMR2
 TIM capture/compare mode register 2, Address offset: 0x1C
 __IO uint32_t TIM_TypeDef::CCER
 TIM capture/compare enable register, Address offset: 0x20
 __IO uint32_t TIM_TypeDef::CNT
 TIM counter register, Address offset: 0x24
 __IO uint16_t TIM_TypeDef::PSC
 TIM prescaler, Address offset: 0x28
 uint16_t TIM_TypeDef::RESERVED9
 Reserved, 0x2A
 __IO uint32_t TIM_TypeDef::ARR
 TIM auto-reload register, Address offset: 0x2C
 __IO uint16_t TIM_TypeDef::RCR
 TIM repetition counter register, Address offset: 0x30
 uint16_t TIM_TypeDef::RESERVED10
 Reserved, 0x32
 __IO uint32_t TIM_TypeDef::CCR1
 TIM capture/compare register 1, Address offset: 0x34
 __IO uint32_t TIM_TypeDef::CCR2
 TIM capture/compare register 2, Address offset: 0x38
 __IO uint32_t TIM_TypeDef::CCR3
 TIM capture/compare register 3, Address offset: 0x3C
 __IO uint32_t TIM_TypeDef::CCR4
 TIM capture/compare register 4, Address offset: 0x40
 __IO uint32_t TIM_TypeDef::BDTR
 TIM break and dead-time register, Address offset: 0x44
 __IO uint16_t TIM_TypeDef::DCR
 TIM DMA control register, Address offset: 0x48
 uint16_t TIM_TypeDef::RESERVED12
 Reserved, 0x4A
 __IO uint16_t TIM_TypeDef::DMAR
 TIM DMA address for full transfer, Address offset: 0x4C
 uint16_t TIM_TypeDef::RESERVED13
 Reserved, 0x4E
 __IO uint16_t TIM_TypeDef::OR
 TIM option register, Address offset: 0x50
 __IO uint32_t TIM_TypeDef::CCMR3
 TIM capture/compare mode register 3, Address offset: 0x54
 __IO uint32_t TIM_TypeDef::CCR5
 TIM capture/compare register5, Address offset: 0x58
 __IO uint32_t TIM_TypeDef::CCR6
 TIM capture/compare register 4, Address offset: 0x5C