B-1
APPENDIX
B
BIOS POST Codes
Note – The information in this appendix applies to all Sun Fire X4100/X4100 M2 and
X4200/X4200 M2 servers, unless otherwise noted in the text.
The system BIOS provides a rudimentary power-on self-test. The basic devices
required for the server to operate are checked, memory is tested, the LSI 1064 disk
controller and attached disks are probed and enumerated, and the two Intel dual-
Gigabit Ethernet controllers are initialized.
The progress of the self-test is indicated by a series of POST codes.
These codes are displayed at the bottom right corner of the system’s VGA screen
(once the self-test has progressed far enough to initialize the video monitor).
However, the codes are displayed as the self-test runs and scroll off of the screen too
quickly to be read. An alternate method of displaying the POST codes is to redirect
the output of the console to a serial port (see Section B.2, “Redirecting Console
Output” on page B-2).
The message, BMC Responding, is displayed at the end of POST.
B.1 How BIOS POST Memory Testing Works
The BIOS POST memory testing is performed as follows:
1. The first megabyte of DRAM is tested by the BIOS before the BIOS code is
shadowed (that is, copied from ROM to DRAM).
2. Once executing out of DRAM, the BIOS performs a simple memory test (a
write/read of every location with the pattern 55aa55aa).
To Next Page
Loading...
